About nmadhavan

nmadhavan · 2014-04-04

Posted on April 04, 2014 at 16:41Hi,I was using connectivity line device(f107) previously and i did clock configuration using filesystem_stm32f10x_cl.c. The configuration wizard attached with this file was really help ful. I am wondering any similar...

nmadhavan · 2014-03-19

Posted on March 19, 2014 at 15:28Hi,I am working on a system using STM 32F107 processor(connectivity line). Because of our requirement same memory location of SRAM is accessed by both CPU and DMA. CPU is supposed to move the data from initial locati...

nmadhavan · 2014-03-20

Posted on March 20, 2014 at 19:16@sung: I am currently not using two DMAs to transfer data. I am just using one DMA which is to transfer data from peripheral to SRAM location A and from SRAM location A to SRAM location B is done by a ''while loop''...

nmadhavan · 2014-03-19

Posted on March 19, 2014 at 20:21 @Sung: you are right.CPU is copying same data multiple times. It is because DMA is not updating the Location A in between the transfer. Both DMA transfer rate and CPU tranfer occurs at 20 Khz but it is out of sync...

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similar to system_stm32f10x_cl.c for low medium, xl density devices?

DMA and CPU accessing SRAM same time

Re: DMA and CPU accessing SRAM same time

Re: DMA and CPU accessing SRAM same time