>>So no such documents... Well, thanks.
I don't know, I've seen presentations about the ART, and I have a reasonable understanding of the underlying architectures in an SoC context. The CM4 doesn't have an architecturally defined cache, ST bolted something on the side to provide a fast prefetch path based on widening the flash read line width, 128-bit as I recall.
It really isn't geared to one-time, non-temporal use, or access via DMA, etc. In the worst case it is going to cause bus contention, likely blocking for 6 cycles or more, per access.
Where documentation is lacking, or of questionable value, one has to read between the lines, apply knowledge of other ARM implementations, and formulate tests to prove or disprove the viability of different methods.
