Posted on July 10, 2017 at 22:04It's one of those five minute apps I write to select gear ratios based on the rules and values the manuals suggest are available. One could arguably do the math when setting PLL rather than using hard coded values, which could make dynamically tuning the power usage easier. ie something you drove from the console rather than rebuilding the code for each test. It would make finding the sweet spot for the application easier, don't be afraid of going faster for a briefer amount of time if the power consumption envelope actually gets smaller rather than running continuously at a slower speed.
I haven't done the profiling work, but I'd expect you'd want to constrain the VCO frequency, so keeping PLL_P as low as possible for the target frequency. Depending on other taps and limited dividers you might want a higher VCO frequency to run other things. It's an asymmetrical pulse generator, which is why you need the DIV2 to get a 50/50 duty.
I would generally pick an HSE frequency that would be my nominal (slower) operating speed, and then switch to that and turn off the PLL. Now in profiling you might want to just disconnect the PLL from downstream logic to see how much that saves, and then look at what just the PLL/VCO contribute. And look at how much time is burned locking the PLL.
