Data Watchpoint on Cortex M3

kr_rahul · ‎2009-08-15

Posted on August 15, 2009 at 11:59

kr_rahul · ‎2011-05-17

Posted on May 17, 2011 at 13:19

Dear sjo,

Thanks again for your reply.

I agree with you that the monitor command for watch-point is not supported by OpenOCD with-respect-to Cortex M3.

However OpenOCD does support setting of hardware watchpoint through the Zn packet, where:

Z2=> read watchpoint

Z3=> write watchpoint

Z4=> access watchpoint

The 'Z' packets are sent by the gdb client when the watch point is applied by the commands:

awatch/rwatch

eg: awatch loop_count =>should set an access watchpoint at variable loop_count

It is implemented by the function cortex_m3_set_watchpoint() in the file cortex_m3.c.

The function cortex_m3_set_watchpoint() duely sets the hardware registers (comparator, mask and function register). The DWT module is also enabled by OpenOCD by setting the TRCENA bit in the DEMCR register. After all this you would expect the cortex m3 to halt when a read/write/access to the specified memory location occurs. However the Cortex-M3 never halts.

Hence if you think that the above function/code of OpenOCD is not correct, then that too needs to be fixed.

However, before attempting to fix OpenOCD it would be worthwhile to know whether anyone has got the watch-point mechanism (provided by DWT unit) to work on STM32 hardware (and not simulator).

Thanks and regards,

Rahul

sjo · ‎2011-05-17

Posted on May 17, 2011 at 13:19

The watchpoint on a address does work - last time i tried it - you just use a mask of 0xffffffff, eg. to break on write.

mon wp 0x20000000 4 w 0 0xffffffff

we have made quite a few changes over the last few months to openocd, so we may have upset a few things. This was mainly for cortex_a8 support.

Cheers

sjo

PS. incase you are wondering i am an admin/dev on openocd.

kr_rahul · ‎2011-05-17

Posted on May 17, 2011 at 13:19

Dear sjo,

Finally I have been able to get the watch-point to work with stm32 using amontec jtag. It seems the issues I was getting were due to the cortex m3 getting in an unknown state.

thanks for your assistance.

-regards