Data validity during DMA transfer

[philipp239955_st]

Posted on February 12, 2010 at 08:43

Data validity during DMA transfer

[Tesla DeLorean]

Posted on May 17, 2011 at 13:40

Your method is hideously prone to race conditions.

Define invalid. The value in the memory location will either be the older value or the new value, depending on how you catch the memory. It's not going to be an undefined state. You should ensure you define the variable as ''volatile'' in C so the compiler is forced to re-read the content every time it is used instead of optimized into a register. One way to mitigate the racing might be to have a significantly larger array (say 9 or 18), read the current DMA address pointer, and read the values in the 3 records immediately behind it (modulo 3). -Clive

[philipp239955_st]

Posted on May 17, 2011 at 13:40

Hi Clive

thanks for your answer. The AD signals I'm measuring are static. Invalid in my special case would be the following: 1. AD conv. = 21.5°C (allredy processed) 2. AD conv. = -200°C (totally undefined) but as you wrote before the value would never be undefined. I don't care about how ''old'' the values are. A conversion of the ADC takes up to several hundreds us (depending on the ADC baudrate). I need the values every 10ms. In that case I don't need the TC-interrupt. I'm going to read the array whenerver I need it. I know that I could do a single conversion instead of running a circular DMA transfer. But that should work for me Phil

[chikos332]

Posted on May 17, 2011 at 13:40

Hi,

I'm curious to know if you will have hard faults when DMA and CPU are accessing the same address simultaneously... It may don't happen for you if the reading/writing frequency is low (or may happen very rarely)... but I'd like to know if it is even possible to happen? and if you might consider this risk. What do you think ?

[Tesla DeLorean]

Posted on May 17, 2011 at 13:40

I think you'll find that the whole DMA operation has to be fundamentally sequenced and arbitrated, if it wasn't things would break very quickly. I don't think there is anything magic about the addresses being the same. How any read/write operations are interleaved will depend on the time when the requests occur and how the bus responds. This can be compounded by things like write buffers. There will be race conditions whenever two sources try to write to a specific locations, or if you try to read a pointer that can change asynchronously.

-Clive