cancel
Showing results for 
Search instead for 
Did you mean: 

configure a general purpose TIMx (x=2,3,4) same as Systick on STM32F103B

slimbahri
Associate II
Posted on March 12, 2010 at 10:33

configure a general purpose TIMx (x=2,3,4) same as Systick on STM32F103B

14 REPLIES 14
Posted on May 17, 2011 at 13:43

#define CPUCLOCK (36.0) // CPU Clock MHz

{

  int i;

  for(i=0; i<10; i++)

  {

    u32 a, b;

    do

    {

      a = SystemTick; // 1ms counter off SYSTICK interrupt

      b = SystemTick;

    } while(a == b); // Sychronize on SYSTICK

    STOPWATCH_START

    Sleep(10); // 10ms delay

    STOPWATCH_STOP

    printf(''%10d cycles, %7.4lf ms\n'',cyc[1],((1.0 / (CPUCLOCK * 1000.0)) * (double)cyc[1])); // 36 MHz clock, milliseconds from cycles

  }

}

    360091 cycles, 10.0025 ms

    360091 cycles, 10.0025 ms

    360089 cycles, 10.0025 ms

    360089 cycles, 10.0025 ms

    360089 cycles, 10.0025 ms

    360091 cycles, 10.0025 ms

    360175 cycles, 10.0049 ms

    360089 cycles, 10.0025 ms

    360177 cycles, 10.0049 ms

    360177 cycles, 10.0049 ms

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
Posted on May 17, 2011 at 13:43

>>with the method you suggested, we should using J-TRACE isn't it ? I have only J-LINK;

The cycle counting works with the trace hardware inside the STM32 core, it *does not* require a J-TRACE or J-LINK. It works with stock STM32F103 devices, and probably the rest of the family.

If the delay routine is using the SYSTICK at 1 ms, then the 10 ms delay could be between 9-11 ms depending on when you catch the counter.

You could always get additional accuracy by using SysTick->VAL which counts down at 1/8000 of a millisecond (assuming 64 MHz, and a /8 prescale, and a 1 ms interrupt)

-Clive

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
Posted on May 17, 2011 at 13:43

Using Timer 4, less resolution/precision, 16-bit register

{

  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;

  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);

  TIM_DeInit(TIM4);

  TIM_TimeBaseStructure.TIM_Period = 0xffff;

  TIM_TimeBaseStructure.TIM_Prescaler = 15;

  TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;

  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure );

  //TIM_ARRPreloadConfig(TIM4, ENABLE);

  TIM4->EGR |= 0x01;

}

{

  u16 tim[2];

  int i;

  for(i=0; i<10; i++)

  {

    u32 a, b;

    a = SystemTick;

    do

    {

      b = SystemTick;

    } while(a == b);

    tim[0] = TIM4->CNT;

    TIM4->CR1 |= 1;

    Sleep(10);

    TIM4->CR1 &= ~1;

    tim[1] = TIM4->CNT;

    tim[1] = tim[1] - tim[0];

    printf(''%10d cycles, %7.4lf ms\n'',tim[1],((16.0 / (CPUCLOCK * 1000.0)) * (double)tim[1]));

  }

  putchar('\n');

}

     22510 cycles, 10.0044 ms

     22510 cycles, 10.0044 ms

     22511 cycles, 10.0049 ms

     22511 cycles, 10.0049 ms

     22510 cycles, 10.0044 ms

     22511 cycles, 10.0049 ms

     22510 cycles, 10.0044 ms

     22510 cycles, 10.0044 ms

     22511 cycles, 10.0049 ms

     22510 cycles, 10.0044 ms
Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
Tomas DRESLER
Senior II
Posted on May 17, 2011 at 13:43

One more argument FOR SysTick:

reading TIMx through APB brings jitter and delay in range (1+ratio) AHB cycles due to resynchronization between APB and AHB in the bridge.

Reading systick is done on internal Cortex bus => very low latency, cycle precise. Btw. even if any jitter might be induced, the whole MCU would be delayed with the same amount of time => it's still cycle precise :)
slimbahri
Associate II
Posted on May 17, 2011 at 13:43

Hi Edison,

Would you explain this with more details please?

Slim