Combination of PLL PREDIV and MUL factors when some frequency is desired

[matic]

Posted on September 25, 2016 at 10:27

Hi.

I have to reduce system clock from 72 MHz to 48 MHz. Input frequency is 16 MHz from external oscillator. I could achieve 48 MHz in two ways:1. With PLL PREDIV = 2 and PLL MUL = 6 or2. with PLL PREDIV = 1 and PLL MUL = 3Is any combination better than other and why? Or the combination of those two parameters is not crucial, as long as desired frequency is achieved?Thanks

[mark239955_stm1]

Posted on September 25, 2016 at 14:02

If the only timebase that you need to worry about is HCLK/SYSCLK then the choice of multipliers and dividers is usually not crucial, although you do need to bear in mind that the PLL may have upper and lower bounds on frequency at several points.  If you need to generate secondary clocks, e.g. a 48MHz clock for USB, then that may constrain your options as well.

[Tesla DeLorean]

Posted on September 25, 2016 at 14:10

Usually further constrain by maximum speed for the VCO, and the range of frequencies supported for the PLL comparison frequency.

You could also output via the MCO pin and review jitter/phase-noise