Clock configuration for stm32l432

[Palitsky.Gennady]

Posted on April 07, 2018 at 03:44

I am working on a project with stm32l432kb. It uses 8 MHz external clock in order to achieve 80 MHz system clock. I've configured clock with the Cube. The diagram shows system clock at 80 MHz, nevertheless the real clock seems to be about 16 MHz. Reading clock with  HAL_RCC_GetHCLKFreq() gives value of 15875000. I've verified that the defined HSE_VALUE is 8 MHz. Here is the Cube generated code for clock configuration:

void SystemClock_Config(void)

{

RCC_OscInitTypeDef RCC_OscInitStruct;

RCC_ClkInitTypeDef RCC_ClkInitStruct;

RCC_PeriphCLKInitTypeDef PeriphClkInit;

/**Initializes the CPU, AHB and APB busses clocks

*/

RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;

RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLN = 40;

RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;

RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;

RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4;

if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

/**Initializes the CPU, AHB and APB busses clocks

*/

RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;

RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;

RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;

PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;

if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

/**Configure the main internal regulator output voltage

*/

if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

/**Configure the Systick interrupt time

*/

HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);

/**Configure the Systick

*/

HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);

/* SysTick_IRQn interrupt configuration */

HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);

}

What can be wrong with configuration?

Thank you

[Dave Jones]

Posted on April 12, 2018 at 20:00

'Shouldn't your PLL_N be set to 10 for VCO clock frequency of 80MHz with PLL clock input as 8MHz and PLL_M=1?'

The output of the PLL is the input clock divided by M, multiplied by N, and then divided by R. Since R can't be one, it must be divided by 2, 4, 6, or 8. So after the multiply by N you need at least twice the final frequency. With an 8MHz input, and M=1, then N must be at least 20, since R can't be less than 2. There are other combinations besides M=1, N=20, and R=2 that will work. But since the SAI1 clock and USB1 clock also come out of that same PLL, and are effected by the choice of M and N, not all possible combinations that provide a sysclk of 80MHz will be desirable.

[Palitsky.Gennady]

Posted on April 12, 2018 at 20:03

If you set PLLN multiplier to 10, the max clock you can get is 40 MHz since the PLLR divider is at least /2.

PLLN = 40, PLLR = 4 will give you 80 MHz 

[Reema O]

Posted on April 12, 2018 at 20:13

Thanks, Dave I complete fought about R factor. As in my implementation I am not using either USB and SAI, I guess I need not worry about other PLL outputs.Also, I notice that in Gennady comment that he is using pin A8 (GPIO) as input for external clock, should that be  necessarily PA0 as it is the only pin which has CK_IN as 'Additional Alternate Funtcion'?

[Imen.D]

Posted on April 23, 2018 at 10:36

Hello,

The issue on CubeMx 4.25 about 

PLLM assignment missing passed along to our CubeMx team for fix in the next release.

Best Regards,

Imen

[Nawres GHARBI]

Posted on April 23, 2018 at 11:00

Hi Palitsky, 

This will be fixed next release, as a workaround you can use the RCC LL driver where the PLLM is well configured

Have a nice day 

[taraben]

Posted on May 29, 2018 at 13:36

Hi all,

could you recheck using CubeMx 4.25.1? The releaseNotes claimes that this is fixed now, but in my project it did not help.

regards, Adib.