Can't disable backup domain write protection in PWR_CR1
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2022-04-22 2:32 AM
Hey there,
I'm trying to access STM32G071's backup register TAMP_BKP0R, PWR_CR1 is set successfully, however I can't store anything in the backup register.
enum backup_reg{foo0, foo1, foo2, LOW_POWER_RESET};
RCC_APBENR1 |= RCC_APBENR1_PWREN_MASK;
/* Disabling backup domain write protection */
PWR_CR1 |= PWR_CR1_DBP_MASK;
/* RTC clock enable */
RCC_BDCR |= RCC_BDCR_RTCSEL_MASK;
RCC_BDCR|= RCC_BDCR_RTCEN_MASK;
TAMP_BKP0R = LOW_POWER_RESET;
Solved! Go to Solution.
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STM32G0 Series
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2022-04-25 4:24 AM
Well, I feared that. Thanks for your efforts, nevertheless!
LW

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