Posting mostly to record some data on a pretty data-free topic.
How long after reset is released does the state of the BOOT0 pin get sampled? On the STM32F413 in particular, but it would be good to know how consistent the spec is.
The official docs always just say "pins are latched on the 4th rising edge of SYSCLK after a reset" (or possibly "of startup clock"), but are never clear on when SYSCLK starts. I figured I had a few 10's of µs to play with, but it turns out I was wrong.
This scenario is not fast enough:
Blue is my BOOT0/NRST signal generation trigger and not important here. Magenta is NRST and cyan is BOOT0.
At the trigger ("T") point NRST is asserted and the STM32 reliably goes into reset (after a <1µs glitch filter). 70µs later I simultaneously release NRST and drive BOOT0 low with the intention of a normal Flash boot. It is not successful, and the STM32 enters the bootloader instead.
The logic thresholds are here:
and my Vdd is about 3.15V. So NRST should de-assert by 2.21V, and BOOT0 should be low by 0.42V. There's appears be not more than a couple of µs before that condition is met, but it is not enough.
On the other hand, if I speed up the BOOT0 transition, I get this:
And normal boot is successful.
So I don't know what the threshold is, but it seems you want the BOOT0 state to be stable very, very soon after NRST is released.
