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ADC skipping samples

DvDriel
Visitor

Dear all,

For a project I'm generating a sin wave with DAC and sampling concurrently with two ADC's. Both DAC and DMA are updated by the DMA. The DAC is triggered by a timer and the two ADC's by another timer.

Details of my setup:

- STM32G491

- DAC3 routed via internal opamp as voltage follower, running at 25MHz in DMA double data mode, trigger source: TIM3 update event.

- ADC1 channel1, ADC2 channel2, both fed by PLLP at 60Mhz, independent mode, continues conversion mode disabled, trigger source: TIM7 update event, 12-bit resolution, 2.5 cycles sampling time, DMA in normal mode.

- TIM3 triggers DAC running at 25MHz.

- TIM7 triggers ADC1 and ADC2, running ideally at ~4MHz.

- APB and AHB busses all running at 150MHz

 

The problem I'm facing is that the ADC's seem to skip some samples at fixed interval as can be seen in the figure below. I can't figure out what's the problem.

DvDriel_0-1761169059519.png

I already have tried the following, all without any changes in the skipping of the samples:

- Lower the triggering frequency of TIM3

- Use continuous conversion mode

- Use a different timer (TIM2, TIM20)

- Disable one ADC

- Change the priorities of the DMA channels

- Swap ADC1 and ADC2

- Lower the clock frequency of the ADC

- Change ADC clock from asynchronous to synchronous

- Increase the sampling time to 6.5 cycles

- Check ADC for overrun events

 

What's weird to me is that the skipped samples seem to always happen around he same two places in the period of the sin wave, even after changing the timing of the ADC. I'm sure however that the sin wave is generated properly (checked with oscilloscope).

Does anyone has any clue what could be the culprit? Many thanks in advance!

 

 

4 REPLIES 4
TDK
Super User

Looks like the effect of hysteresis from something, perhaps a Schmitt trigger. In which case the ADC is correctly reflecting reality. Are these hooked up to any pins in input mode?

> checked with oscilloscope

Can you show? Checked with an FFT or just by eye?

 

Is this a custom board? Is VDDA and VREF+ set up correctly?

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MasterT
Lead

DAC is 15 MSPS max. DMA can't run >14 msps (verified on G474re 170 MHz), so you have to use DAC in double mode to overdrive DAC.

And better to assign another DMA for adc's, having one DMA exclusively for DAC.

 

Thank you for the correction, you're right, I'm indeed using DAC in double data mode (corrected my post). Also your comment on the DMA is valid and that's indeed what I did, DMA 1 serves both ADCs and DMA2 the DAC.

Thank you for thinking with me here! The ADCs are on pins PA0 and PA1. It's a custom board and yes, VDDA and VREF should be fine, I'll double check.

I checked the DAC output simply by eye, but could still run a FFT to make sure the spectrum doesn't contain any weird artifacts.