The Raspberry Pi Pico 2W is a dual-core Cortex-M33 processor. It has 16 DMA channels per bus. While I'm not sure if the exact number represents all DMA channels, there's only one path each for the master and slave. Therefore, if three modules occupy the DMA, there's a delay of nearly a second when switching processes using FIFO messaging.
The B-U585I-IOT02A, an STM32 development board, has a single Cortex-M33 core. According to sources, even with a single core, the bus is multi-layered for DMA, so there should be no delay. This is called a bus matrix, and the attached datasheet shows multiple arrows in the diagram, arranged like a matrix. If this is a valid interpretation, I wonder if it would work well when switching from TCP communication to I2S, or from I2S playback to TCP communication.
The Raspberry Pi Pico 2W is dual-core, so I don't need to implement multithreading. I2S, FatFS, and TCP communication are all allocated to each core, so it works fine without threading. To eliminate the 1-second delay, I looked into the B-U585I-IOT02A, but it only has one core. I'm considering it because I heard it has a smoother bus, but if it doesn't match the description, I'll end up spending over $100, so I'm asking.
Will a streaming audio player run smoothly on the B-U585I-IOT02A?
