APB1ENR Power interface clock enable bit

[Ravindra Waghode]

Posted on June 07, 2018 at 09:36

I am using stm32F0 and Stm32L0 series MCUs.

APB1ENR in Stm32 has Power interface clock enable bit (Bit 28). I have gone through the reference document to unserstand what is its significance.  

Bit 28 PWREN: Power interface clock enable

Set and cleared by software.0: Power interface clock disabled1: Power interface clock enabled

Please help me to understand it. 

[waclawek.jan]

Posted on June 07, 2018 at 10:45

It enables registers described in chapter Power control (PWR).

JW

[Ravindra Waghode]

Posted on June 07, 2018 at 11:00

Hello Sir,

Could you please help me understand how it enables the 

registers described in chapter

Power control (PWR)?

Thanks,

Ravindra

[waclawek.jan]

Posted on June 07, 2018 at 11:07

If you don't set the RCC_APB1ENR .PWREN bit, the registers of PWR unit can't be written and reading them returns 0.

JW