Any ideas with regard to spurious ADC values

[Lorne Vaasjo]

Posted on February 27, 2017 at 20:05

I am using the ADC+DMA to collect samples for AC power calculations.  The voltage and current are well buffered (low impedance sources) sampled at about 7kHz.

The data acquisition will work properly for many seconds (between 10 and 40) but then I will get a series of ADC readings in the raw data that are completely incorrect.

To try to figure this out I am collecting the raw ADC values in a buffer that collects one second of data and gets re-written until a spurious value arrives.

The following is a part of the raw ADC buffer showing spurious data in samples 58 through 70.

I have experimented with different sample rates, buffer sizes and adc settling times but haven't found anything that gets rid of the problem.

The processor used is an STM32F030CCT6 using a 28MHz external crystal.

The 'raw values' below are relative to the prevous 1 second average value for each reading (thus the negative values) and the sample rate is lowered from the 7kHz.

sample#, rawVolts, rawCurrent, v*i/100

26,78,-1,0

27,171,-1,-128,269,-1,-229,358,0,030,544,2,1031,537,-1,-532,494,-2,-933,429,-1,-434,353,-1,-335,277,0,036,180,-1,-137,68,0,038,-35,0,039,-125,0,040,-223,-1,241,-317,-2,642,-396,-2,743,-453,-2,944,-500,-1,545,-529,-1,546,-541,-2,1047,-541,0,048,-521,-1,549,-463,-1,450,-391,-1,351,-316,-2,652,-231,-1,253,-123,-1,154,-14,0,055,80,0,056,174,1,157,272,-1,-258,360,1990,716459,-1488,1991,-2962660,-1991,1939,-3860561,-1991,1991,-3964062,-455,-960,436863,-1133,-1986,2250164,-1987,637,-1265765,461,1931,890166,-1931,11,-21267,859,-1990,-1709468,-1991,295,-587369,-545,5,-2770,-1931,-1,1971,-33,-1,072,-124,0,073,-222,-1,274,-317,0,075,-396,-2,776,-451,-1,477,-499,-1,478,-529,-1,579,-541,-1,580,-542,-1,581,-519,0,082,-464,-1,483,-392,-1,384,-316,-1,385,-232,-2,486,-124,-1,187,-15,0,088,80,-1,089,173,0,090,270,-1,-291,360,-1,-392,439,2,893,477,-1,-494,518,-2,-1095,536,-1,-596,544,-1,-597,536,0,098,498,0,099,430,0,0100,355,-1,-3101,278,0,0102,179,-1,-1103,67,-1,0104,-31,-1,0105,-124,-1,1106,-222,-1,2107,-316,0,0108,-396,-1,3109,-451,0,0110,-499,-2,9111,-529,-1,5112,-542,-1,5113,-541,0,0114,-521,-1,5115,-464,-1,4116,-392,-1,3117,-318,0,0118,-232,-1,2119,-124,-1,1120,-16,-1,0121,79,0,0122,171,0,0123,270,-1,-2124,359,-1,-3125,427,-1,-4126,475,-1,-4127,517,-1,-5128,536,-1,-5129,544,0,0130,536,-1,-5131,498,0,0132,432,0,0133,354,0,0134,280,-2,-5135,181,-1,-1136,69,-1,0137,-33,-1,0138,-124,-1,1139,-220,-1,2140,-315,0,0141,-395,-1,3142,-451,-1,4143,-498,-1,4144,-528,-1,5145,-541,-1,5146,-541,-1,5147,-524,-1,5148,-466,0,0149,-391,0,0150,-318,1,-3151,-232,-1,2152,-125,-1,1153,-16,-1,0154,78,-1,0155,171,-1,-1

[Tesla DeLorean]

Posted on February 27, 2017 at 21:55

Are you managing the buffer in a ping-pong fashion, with HT and TC interrupts, so that you are not doing analysis of live data that might be changing via DMA action on the buffer in the background?

[S.Ma]

Posted on February 27, 2017 at 22:09

What happen if you scan only one channel?

Activate the analog watchdog to see and even stop as soon as the weird values are detected.

By toggling a GPIO to make a pulse when the weird values are detected, analog check can be done using an oscilloscope.

[Lorne Vaasjo]

Posted on February 28, 2017 at 01:11

I'm using a circular buffer and processing the oldest half of the data buffer on both complete and half-complete dma interrupts. I am using the correct half of the buffers as well.  I put a port line high during the processing and the processing time is about 1/20 of the collection time so I'm not ever accessing data that's changing. I also keep track of the worst case number of clock ticks that occur during the processing and that indicates the processing never takes extra time.

[Lorne Vaasjo]

Posted on February 28, 2017 at 01:56

I haven't tried using a single channel but have jumpered one input to an extra channel to see if the values track. They do track except when strange data occurs which indicates the issue is likely and internal one and not an issue with the voltage on the pin(s). I need to do some further testing to be sure that is always the case.

[S.Ma]

Posted on February 28, 2017 at 07:19

By using the analog watchdog, it will tell if the problem is on the ADC side or it is a memory bus bandwidth or wrong free SRAM area. 

[AvaTar]

Posted on February 28, 2017 at 09:07

The data acquisition will work properly for many seconds (between 10 and 40) but then I will get a series of ADC readings in the raw data that are completely incorrect.

Excluding a DMA vs. core access issue (as Clive One suggested), that sounds like some race condition.

Perhaps this 10 .. 40 seconds is about the time for two events (interrupts ?) to overlap statistically.

Either another handler takes too long, or there is some kind of bus contention that keep the DMA from picking up the ADC value.

Have you checked the errata ?