Any iDea on using Circular Buffer for DSP application

Posted on October 06, 2013 at 23:28

To start I assume you are using an M4 with the DSP extensions.  If you are capturing a waveform at a high data rate you'll need to balance your DMA bus access to maximize overlapping operations for the optimum thruput rate.

Set up your ADC capture with dual or triple ADC units if possible, This gives you parallel ADC conversions and in the case of paired ADCs (ADC1 and ADC2) it effectively doubles bus efficiency by transferring a 32 bit word at a time instead of 2 separate 16 bit transfers.  With the DMA FIFO you can burst 4 words (8 samples) at a time into SRAM.  Even if you can only do sequential sampling on one unit make sure you align the buffer to DMA 1KB boundaries and take advantage of the DMA FIFO to pack and unpack 16 bit samples into 32 bit words.

Set up the DMA as a circular buffer with interrupts at half transfer (HT).  The destination buffer should be in SRAM1 to take advantage of D-cache lines since you are doing sequential transfers.  On each HT do your data reduction with the DSP extensions.  Use SRAM as one operand (X) and the CCM as the second operand (Y).  Place the destination result back in CCM (Y) if you're using some type of accumulate operation (i.e. Y = Y * X).  Remember, any flash or CCM memory access will run in parallel with DMA, no cost for bus access and no DMA bus contention.

The HT will guarantee you have a complete half buffer so that a D-cache read at the start of a line will prefetch 128 bits (4 words, 8 samples).  Don't use the DMA address register to track available data unless you stop DMA.  Don't use SRAM2 as it isn't cached.

Using CCM as the second operand space allows DMA overlap to SRAM1 while accessing CCM.  Make sure your task stack and any other non-DMA variables are in CCM too.

  Jack Peacock

Posted on October 09, 2013 at 16:08

Thanks Peacock for detailed answer actually I am not much experienced with this STM series.

I think by telling you my task will help me in getting more compact ideas by you.

First of all I am implementing a FM Receiver over Software Defined Radio for my Final Year Project. So we are going to receive a frequency of 88-108MHz which is processed by some intial stage hardware converting the stage to 360KHz after two times down conversion. In DSP, I am just trying to make FM detection algorithm, which is primarily based on PLL based detection.

In this section I have to implement three most common things like:

1)Multiplier asBalanced Modulator

2) Low Pass Filter.... to get the difference between the two signals one from ADC (360KHz) signal and another from the built-in oscillator (NCO), by removing high frequency part from the multiplier output.

3) Generation of Sine/Cosine Wave by the feedback of Low Pass Filter's Output, just like a discrete time VCO i.e. NCO, the output of NCO is connected to other input of Multiplier.

Sir, my achievement till now is that I am able to complete initial setup for ADC,DAC,DMA,RCC,TIM,etc. though it is inefficient till now. I also have implemented ROM Based Cosine Wave Generation, and designed the Discrete Low Pass Filter using FDATOOL (MATLAB).

Many of the things are unclear to me till now, and some of them includes, single precision processing, efficiency of generated code, etc.

I have to maintain a sampling frequency of 4 MHz according to my design/model.

I am attaching my design report along with the work done on DSP Processor (STM32f303VC) until yet.

Thanks.

Umair Mukati.

________________

Attachments :

ADC_DAC.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1Ii&d=%2Fa%2F0X0000000blj%2FX6_Ztph38jVTIUPQEyL_u1ihsx8uxFixcdvX2pFp8vw&asPdf=false

Design_Report.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1Lv&d=%2Fa%2F0X0000000bli%2F_zYk851VeSUvpR3dHMehAEXjwvnSad1NDqrTky2_4Ts&asPdf=false