Hello,
my intention is to catch a 'thin spike' from the input analog signal. Therefore I wish the sample times from 2 ADCs may cover echo other's conversion time, so that the thin spike will not be missed.
My plan is to use 8.5 cycles for sampling and 8.5 cycles for conversion.
How ever on page 975 of RM0433, it states there need to be at lease 1 ADC clock cycle delay between the interleved samples.
I believe missing 1 cycle from each (8.5+1) cycles may not be a big issue(a capacitor will probably amend it), but this 1 cycle makes the intened 17 cycle interleved mode invalid.
Q1: is there a way to program a "wait cycle" in continuous conversion mode?
Q2: if Q1 is not possible, what may happen if I connect the input analog signal to both of the ADCs, and let them work independently? Will the ADCs get sample data correctly? In this case, what can be done to make sure the 2 individual ADCs are interleved?
Of the analog signal, the OpAmp can be designed so that adequate driving current can be provided to the 2 ADC channels.
Thank you!
