About power consumption, how much is it influenced by the RAM usage?

[Lingjun Kong]

Posted on August 18, 2017 at 18:30

I know in some RAM components, there is many blocks in it and the more the memory usage is required, the more blocks it open for the algorithm. So that the power consumption is also increased.

So for ARM-Cortex M chip, for example STM32F series, how much power consumption the RAM component has taken in the whole system, is there an existing manual?

[Tesla DeLorean]

Posted on August 18, 2017 at 19:03

Reading is going to consume less power than writing content, but strongly driven by your access patterns and churn.

There is going to be some static consumption based on the size of the array, but the bulk of the consumption will be you accessing it and executing code, and I'm not sure that's going to be easy to separate out.

Look also at SLEEP current, where the core isn't doing much, and bulk is going to maintain internal state.

>> is there an existing manual?

Perhaps one on CMOS VLSI Design? I'm sure ST's design tools can estimate currents at a gate level for various sections of the chip design.

[Lingjun Kong]

Posted on August 18, 2017 at 22:14

The design tool you mentioned is CubeMX? There is a power consumption calculator but I think it is just a component level evaluator. 

[Tesla DeLorean]

Posted on August 18, 2017 at 22:56

No, it would be IC design tools, like the silicon compiler creating the RAM array cell, based on characteristics for the process/geometry.

[Lingjun Kong]

Posted on August 18, 2017 at 23:00

I'm not very sure what you said. Does ST provide a gate level design tool for public? 

[Tesla DeLorean]

Posted on August 19, 2017 at 01:48

In the general sense the amount used by the SRAM is going to be fractional compared to the CPU.

At a system level you're going to need to watch what you're connected too, because getting the signals off the chip is going to burn a lot of energy. For instance if you leave an LED energized, or you export a 25 MHz clock banging up and down with a fast slew rate, in to a capacitive load (ie resistant to change)

[Tesla DeLorean]

Posted on August 19, 2017 at 01:35

Ok, but you ask a question that supposes some understanding about the construction of the device.

If you have a specific device, with a specific memory configuration in mind, perhaps you can ask ST for details about that. They aren't likely to provide chip tools, or gate level details.

The Data Sheets should have some speed, voltage, function breakdown for the parts. Not sure it is decomposed in a way that separates the CPU and RAM, or different RAM configurations. As you can't turn if off it is lumped in with the CPU in a per/MHz cost, some have execute SRAM vs FLASH, where the FLASH uses more power.

It's going to consume less than some of the other components likely on the board in the static case.

May be you can frame the question differently, describing your system, its function and your power goals.

If you are using HAL/CubeMX a large amount of your power will be wasted in blocking loops like HAL_Delay() or peripheral polling loops with timeouts.

[Lingjun Kong]

Posted on August 19, 2017 at 11:03

Thank you very much. and the final question, in general, when you working a project (make a software on a specific device), how would you predict the power consumption? work it out and measure it or calculate it by adding the components together? What about the CPU? if, for example, a cortex-m chip, it works on a constant frequency without sleep, the power consumption is always the same?