6Steps example

[michaellange9]

Posted on July 04, 2008 at 08:06

6Steps example

[michaellange9]

Posted on May 17, 2011 at 12:38

Hi,

I don't understand in which way the example code (STM3210B firmware Version June 2008) works. How is the output-pattern generated? For my understanding i.e. CC1 and CC1N are enabled at the same time (block 2)?!? ... if (step == 1) { /* Next step: Step 2 Configuration ---------------------------- */ /* Channel3 configuration */ TIM_CCxCmd(TIM1, TIM_Channel_3, TIM_CCx_Disable); TIM_CCxNCmd(TIM1, TIM_Channel_3, TIM_CCxN_Disable); /* Channel1 configuration */ TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_ForcedAction_Active); TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable); TIM_CCxNCmd(TIM1, TIM_Channel_1, TIM_CCxN_Enable); /* Channel2 configuration */ TIM_SelectOCxM(TIM1, TIM_Channel_2, TIM_ForcedAction_InActive ); TIM_CCxCmd(TIM1, TIM_Channel_2, TIM_CCx_Enable); TIM_CCxNCmd(TIM1, TIM_Channel_2, TIM_CCxN_Enable); step++; } else if (step == 2) ... Can anyone tell me in own words, how this lines are working? Especially how are the output pins are forced? General, are flowcharts for the examples available? Thanks in advance!

[michaellange9]

Posted on May 17, 2011 at 12:38

I'll try to explain it by my own. Please correct me!!!!

This code-block preloads the timer-configuration for step 1. When an COM-event occurs, this configuration will be overtaken. - Channel 3 is completely disabled - Channel 1 is forced in active mode (means CC1=1 and CC1N=0?? although OC1N is config. to active high?) and Output CC1 and CC1N are enabled. What I don't understand is, that CC1 and CC1N have the same polarity-configuration (both active high; CC1P = CC1PN = 1)?!? Has CC1N always the opposite Level than CC1? In this case disable CC1N would be a possible solution, too? - Channel 2 is forced in inactive mode. I have the same understanding problem like with Channel 1...

[lanchon]

Posted on May 17, 2011 at 12:38

take a look at figure 75 page 217 of the family manual.

-OCxREF is active high -outputs of the CCxNE/CCxE muxes are active high (high supposedly turns on the external power switch) -output of the CCxNE mux is in phase with OCxREF (not inverted) when CCxNE/CCxE is ''10'', as shown. -output of the CCxNE mux is out of phase with OCxREF only when CCxNE/CCxE is ''11'' (OCxN_DT is ''inverted''), but is still conceptually active high. (when CCxNE/CCxE is ''11'', OCxN turns on its power switch when OCx turns its own switch off; that is, they are out of phase.) (this overloading of the line enable bits with the function of selecting whether to use the dead-time generator is an extremely bad design call, IMHO. this choice plus one other bad call that I won't get into makes the macrocell useless or at least very dangerous for many applications.) > Has CC1N always the opposite Level than CC1? this should be clear now. from the manual: Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. [...] From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: -The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. -The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge.

[michaellange9]

Posted on May 17, 2011 at 12:38

ähm... while I do my documentation I found some inconsistency

just a few remarks to the 6steps example code: - CCR1..3_Val is not used and needless - defining TIM_OCInitStructure.TIM_Pulse is not necessary I think - Channel states are one step shifted. IRQ_Handler: Next step should be preloaded like it is written in the comments but not done...

[michaellange9]

Posted on May 17, 2011 at 12:38

Great! Now I think I got it. Thank you very much lanchon.

... a short summary: - OCxN is always the opposite of OCx - OCxREF is created by the ''output mode controller'', chosen by bit OCxM - Every channel has its own OCxREF line - OCxE and OCxEN enables the outputs, but doesn't define the output-level, except the output is disabled, then the level is LOW - The output level is derived from OCxREF. (i.e. OCREF=1 -> OCx=1 OCxN=0) - Except the polarity bit negates OCREF when OCxP=1 or OCxNP=1. So it is possible to annul the negation of OCxN (makes sense i.e. when high side stage is high-level sensitive and low side stage is low-level sensitive..?!?) - Dead-Time generator delays the rising edge of the OCREF-signal -> OCx_DT and OCxN_DT ... I agree with you, ''...overloading of the line enable bits...''

[lanchon]

Posted on May 17, 2011 at 12:38

hi,

>- OCxN is always the opposite of OCx no. what are OCxN and OCx, the output pins? they are sort of in-phase, except when they are derived from OCx_DT and OCxN_DT, in which case they are out of phase. this happens only when both lines are enabled. **see the diagram I referred you to.** >- OCxE and OCxEN enables the outputs, but doesn't define the output-level, except the output is disabled, then the level is LOW better if you substitute LOW for INACTIVE, these signals can't be observed so you don't need to assign a voltage level to them, or a polarity. OCxE and OCxEN do define ''output level'': when both are set, the negative side is inverted (for being derived from OCxN_DT). but don't think of this as a change in polarity, rather as change in significance: the negative side is active when the positive side is inactive; they are out of phase. (if you need to define a polarity, assume that both are active high no matter what values are configured in the enable fields.) >- Except the polarity bit negates OCREF when OCxP=1 or OCxNP=1. So it is possible to annul the negation of OCxN (makes sense i.e. when high side stage is high-level sensitive and low side stage is low-level sensitive..?!?) think of the polarity bits as adapters to match the external hardware. inside the peripheral there's no polarity: signals are abstract entities that are either active or inactive (polarity is an implementation detail that you can't observe and shouldn't be concerned with). when the signals are outputted via actual pins however, polarities must be assigned to the abstract levels. that's what the polarity bits do. (don't think in terms of ''annul the negation'' since signals are not negated cause they have no polarity. they might be out of phase, though.) look at the diagram and carefully reread my previous post. cheers!

[michaellange9]

Posted on May 17, 2011 at 12:38

Hello lanchon,

Its new for me to speak about inactive instead of low, but it makes much more sense. Now, I'm able to change the output pattern and dead time like I want and I think I know what I'm doing ...roughly. That feels good. Thanks a lot! Cheers

[michaellange9]

Posted on May 17, 2011 at 12:38

... back to the firmware:

Why is it important to configure the channels in the right order and what is the right order? It is not working correct when I configure in every step channel 1 first, then channel 2 and at the end channel 3. It seems like a timing problem. i.e. OC1 (output Pin) and OC1N have different duty cycles ?!?