Posted on May 17, 2011 at 12:47thanks design6, I'll email you.
I wanted to mention a few thing about your init sequence. (these comments come from memory, so they might be wrong.) here's a section:
/* Flash 2 wait state */
FLASH_SetLatency(FLASH_Latency_2);
...
/* Select PLL as system clock source */
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
...
/* configure PCLK2 */
RCC_PCLK2Config(RCC_HCLK_Div1);
/* configure PCLK1 */
RCC_PCLK1Config(RCC_HCLK_Div2);
/* Enable Prefetch Buffer */
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
...
/* Enable Clock Security System(CSS) */
RCC_ClockSecuritySystemCmd(ENABLE);
I think I remember that the flash prefetch must be enabled in order to use 2 cycle latency, so that configuration should be moved to the top (but maybe I'm wrong). I don't know what's the default value for PCLK1, but if it's RCC_HCLK_Div1 then you'd be briefly overclocking the peripherals on that bus. I'd move the PCLKxConfigs up before switching over to the fast PLL clock to be on the safe side. and enable CSS before switching to an external clock too, be it direct or via the PLL; that'll guarantee coverage.
