I have a question about SVC.
I am currently implementing an OS service call using an SVC.
When other interrupts and SVC interrupts occur at the same time and the other interrupts are executed first, it seems that the SVC interrupts are not pending.
In other words, the SVC interrupt is not executed after the other interrupt.
The situation is as follows.
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Using board : nucleo l4r5zi
Using interrupts : SVC (priority 5, sub-priority 0)
USART 2CH (priority 5, sub-priority 0)
※ The code is simpler than it actually is.
OS_service_call()
__asm volatile(" SVC %0 \n" : : "I" (0));
__asm volatile(" NOP \n");
uint32_t g_icsr
SVC_Handler()
g_icsr = SCB->ICSR;
～～
USART_2CH_Handler()
g_icsr = SCB->ICSR;
if (g_icsr == 0x0x0000b836) {
__asm volatile(" NOP \n");
}
～～
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Currently, it looks that USART 2CH interrupts are generated when executing "__asm volatile(" SVC %0 \n" : : "I" (0));".The value of g_icsr (= ICSR register of SCB) in USART_2CH_Handler() was 0x0000b836.
VECTPENDING : 0xb → SVC is pending
VECTACTIVE : 0x36 → USART2C interrupt is currently being executed
I considered that SVC-related interrupt requests might have been cancelled,
so I set a breakpoint at "__asm volatile(" NOP \n");" in the if statement of USART_2CH_Handler() to check the behavior when the icsr is 0x0000b836.
When it stops, SCB->ICSSR is 0x40b836 and ISRPENDING is set to 1.
I think that stopping here means that the value of SCB->ICSR was 0x0000b836 until it stopped.
From there, when I did the step execution, the execution of SVC_Handler() started as soon as the execution of USART_2CH_Handler() finished.
I am wondering if the ISRPENDING not being set to 1 is the reason why the SVC interrupt is not pending.
The behavior of ISRPENDING is different when it is broken once and when it is not broken.
Is there any timing or other condition for ISRPENDING to be set?
