Not an issue, just a recommendation for ST HAL developers...
STM32H7 firmware package, SPI_Receive (polled) does not consider the state of the SUSP flag.
During a polled SPI transfer that is larger than the receive fifo size, if the code is pre-empted (maybe a long interrupt or task switch) and the SPI rx fifo fills up, the SUSP flag is set and automatic clocking of SPI data is suspended. The SPI transfer stops. When handing returns to the SPI_Receive function, it reads the rx fifo, then hangs waiting for more data which will never come due the SPI clock being suspended. Eventually the function times out and returns error.
I would recommend clearing the SUSP bit after each reading of the fifo to kick off data transfer again.
I don't need a workaround, just wanted to bring this to attention as could be quite confusing for some people who expect a blocking transfer to never timeout when in master mode.
