STM32H745 – Is it possible to STOP and then restart Cortex-M4 from Cortex-M7 (software only)?

[mrctmgr]

Hello,

I am working with STM32H745 (dual core Cortex-M7 and Cortex-M4) and I am trying to understand the correct and supported way to stop and then restart the M4 core from the M7 core using software only, without resetting the whole chip.

My goal is to implement a core-local watchdog mechanism where the M7 core keeps running and supervises the M4 core. If the M4 gets stuck or stops responding, the M7 should be able to stop or reset the M4 and then start it again cleanly.

I have read the reference manual and found the following:

SYSRESETREQ via AIRCR triggers a full system reset, so it is not suitable for this use case.

Disabling RCC clocks does not actually stop the Cortex-M4 core execution.

HAL_PWREx_ReleaseCore(PWR_CORE_CPU2) only releases CPU2 from the HOLD state and does not reset or stop a running M4 core.

I found the MP_GRSTCSETR register and the M4 reset bit mentioned in some discussions, but the CMSIS and HAL naming is confusing and it is not fully clear whether this is the recommended and safe way to reset only the M4 core at runtime.

I also looked at ST examples where M4 is held in STOP mode during boot and released by M7 using HSEM, but those examples mainly cover boot-time scenarios and not runtime recovery.

My questions are:

Is it officially supported to reset only the Cortex-M4 from Cortex-M7 at runtime on STM32H745?

If yes, is using MP_GRSTCSETR (M4 reset bit) the correct and recommended method?

Is there a supported way to put the M4 core into STOP mode from M7 and later wake it up again?

Is there any ST-recommended architecture for implementing a core-local watchdog on STM32H7 dual-core devices?

I want to avoid undefined behavior and follow the intended hardware design.

Any clarification or reference to an official ST application note or example would be greatly appreciated.

Thank you.

[lobna]

Dear @mrctmgr 

No, there is no officially supported register like MP_GRSTCSETR on the STM32H745 to perform a hard reset of only the M4 core from the M7. This register is specific to the STM32MP1-style RCC and does not exist in the STM32H745/755/747/757 family.

Instead, a software-based restart of the M4 core can be implemented by performing a vector-table jump. For example, the M7 core sends a “restart request” to the M4 core via IPCC, mailbox, or a shared flag.

Upon receiving this request, the M4 core should:

1- Stop all running tasks and disable local interrupts.
2- Re-initialize its stack pointer (MSP) and vector table offset register (VTOR) to the reset values defined in the M4 firmware.
3- Jump to its reset handler, which is the same entry point executed during a hardware reset.
This approach can simulate a reset of the M4 core without requiring dedicated hardware reset registers.

BR

Lobna

[MM..1]

worthless info except no register exist

 If the M4 gets stuck or stops responding,..

But @mrctmgr design sw for hangs isnt best way. Best approach is use advanced watchdog = store state H7 or H4 based who hangs and after full reset continue based on state = no lost. For this is here watchdg ISR and reset source regs.

[mrctmgr]

Thank you for your replies. However, in my use case, the reset mechanism is intended specifically for scenarios where the Cortex-M4 core crashes or becomes unresponsive. In such cases, I want to reset only the M4 core while allowing the Cortex-M7 core to continue running without interruption. For this reason, using a hardware watchdog is not suitable for my design, since it would reset both cores. Instead, I am looking for a software-controlled method that allows the M7 core to recover the M4 core independently.