STM32H503 TIM1--Combine output compare mode and up/down counting mode to generate PWM output

[ellis]

Hi:

I want TIM1 of STM32H503 to output PWM output.

What I need is:

*  the counter works in up/down counting mode

*  Set channel 1 to active level on match (TIMx_CNT match TIMx_CCR1) when the the counter is counting up

*  Set channel 1 to ainctive on match (TIMx_CNT match TIMx_CCR1) when the the counter is counting down

But neither PWM mode  nor Output Compare mode satisfy my requirement. 

* PWM mode  (OC3M[3:0] = 0110b or 0111b):  channel 1 is active/inactive as long as TIMx_CNT<TIMx_CCR1 else inactive.  It means the comparator is always working.  Instead my need is set/clear the channel1 only when TIMx_CNT match TIMx_CCR1.

* Output Compare mode (OC3M[3:0] = 0001b or 0010b):   Set channel 1 to active/inactive level on match.  This mode seem more suitable for my case. But unfortunately it doesn't cover all my requirement: I want the Output Mode Controller take different action on counting up and counting down,  as stated in the beginning of this post.

(Note that OC3M[3:0] = 0011b is Toggle mode.  It's possible that the output is toggled twice when counting up, which is unacceptable for me.)

Could you please tell me how to implement the desired pattern in STM32H503 Advanced Timer1?

*  the counter works in up/down counting mode

*  Set channel 1 to active level on match (TIMx_CNT match TIMx_CCR1) when the the counter is counting up

*  Set channel 1 to ainctive on match (TIMx_CNT match TIMx_CCR1) when the the counter is counting down

[ellis]

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(Note that OC3M[3:0] = 0011b is Toggle mode.  It's possible that the output is toggled twice when counting up, which is unacceptable for me.)

 

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Let me make this more clear: 

 In my case the  TIMx_CCR1  preload is disabled on purpose.

And TIMx_CCR1  may  be written for many times in the half period (up counting or down counting duration).

But the output signal  should only toggle once in half period.

For example, when counter is up counting  the output should transit to 1 from 0 for only once time (or keep high for the half period) . When counter is down counting  the output should transit to 0 from 1 for only once time (or keep low for the half period).   

[ellis]

(Note that OC3M[3:0] = 0011b is Toggle mode.  It's possible that the output is toggled twice when counting up, which is unacceptable for me.)

 

Let me make this more clear: 

 In my case the  TIMx_CCR1  preload is disabled on purpose.

And TIMx_CCR1  may  be written for many times in the half period (up counting or down counting duration).

But the output signal  should only toggle once in half period.

For example, when counter is up counting  the output should transit to 1 from 0 for only once time (or keep low for the half period) . When counter is down counting  the output should transit to 0 from 1 for only once time (or keep high for the half period).   

(There are typos in the above reply.)

[TDK]

> Set channel 1 to ainctive on match

Huh?

The timer cannot be set to different modes depending on up/down counting.

If you show the output you want, there is probably a way to achieve it.

[waclawek.jan]

> If you show the output you want

+1

> there is probably a way to achieve it.

Or not. The hardware can't do what it can't do. Not everything can be worked around through software/DMA/whatnot.

> The timer cannot be set to different modes depending on up/down counting.

Asymmetric mode works differently on up/down counting (btw. combined mode mentioned in title and nowhere else does not), but as far as I understand the problem "description" it won't cut it either.

JW

[Billy OWEN]

Hi @ellis 

This post has been escalated to the ST Online Support Team for additional assistance.  We'll contact you directly.

Regards,

Billy