Posted on October 04, 2012 at 14:26For setting of the divider, which determines the Ethernet MAC-to-PHY Serial Management Interface's (MDC/MDIO lines) clock rate, the stm32f4xx.h header says the following:
&sharpdefine ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
It then goes on listing exactly
5 cases... last of whose is:
&sharpdefine ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
A look into the user manual, ETH_MACMIIAR.CR bits description, reveals, that there are
4 legal values for this field, and the value from the above line is reserved. And, of course, the example code from STM uses exactly this value (as HCLK is set to 168MHz there).
For a definitive answer, let's have a glimpse into the datasheet: Table 64 is the one we are looking for, and it states for both minimum and maximum MDC clock: ''TBD''.
I don't really want this to be commented, just expressing my disgust.
JW
#mdc #mii #smi
