STM32F4 USB DMA fault AHBERR with buffer destination in RAM Area 0x10000000

[c2]

Posted on October 02, 2013 at 15:11

Hi, 

I have some DMA problems with USB HS  in Hostmode on STM32F4. I use USB Library V2.1.0 and set up USB HS with internal PHY in Host Mode and MSC., USB FS in Device Mode and MSC.If Compiler (Keil UVision) sets all _Core_Handle and _Host in Memory area above  0x20000000, all works fine. If Compiler use Memory Area 0x10000000 , DMA of USB Core crashes with AHBERR and no change to get out from  USB HS interrupt routine.This is always when DMA points to a OUT buffer in second RAM area 0x10000000.If i set the core Handles via __attribute__ in the 0x20000000 Area, it works as long as a Buffer in 0x1 Area will be used at example USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer, which is not in 0x20000000 Area.I tried many days to find out this Bug ( USB Sample works cause compiler uses only 0x2 Area for variables, integrated in a bigger project compiler aligned all usb related variables in 0x1 Area and usb crashes), and it seems it is  a  Hardware Problem with integrated DMA in USB Core not described in STM32F4 errata sheet. Do anyone have  experiences with this problem or found a solution without align related variables per hand into 0x2000000 RAM area??Thanks for helpChrisi  #ccm #stm32f4-usb-host-dma-crash

[jpeacock2399]

Posted on October 02, 2013 at 16:02

On the F4 series the CCM is directly coupled to the core through the D-bus and is not accessible from the DMA units.  If you look at the bus diagram in the Reference Manual (page 60 in Rev 5) it shows that the CCM is not connected to either the AHB or APB bus, so the DMA unit has no path to that region of memory.

This is actually a feature, not a design error.  DMA can overlap CCM memory access by the core without a bus collision.  I make frequent use of it, running high bandwidth DMA to SRAM in parallel with computations out of CCM.  It has an advantage in DSP operations on the M4 too, where one operand and the result go to CCM while the second operand comes from SRAM.  This means you can stream in signal conversions with DMA from the ADC circular buffers and process half buffers on the fly with minimal bus contention, especially if you make use of DMA with FIFO and burst mode.  You can see the same architecture in DSPs where memory is segmented into separate banks, one to capture signals and the other to hold results as the DSP performs a multiply and accumulate operation.   Jack Peacock

[c2]

Posted on October 02, 2013 at 16:26

Hi Jack,

thank you for your reply! You are right! After many days tried to understand working of USB firmware and to get both USB cores working in a different way ( as master and host), brain was burned out. Seems the only way is to avoid compiler use CCM for DMA depend variables.Greetings!Chrisi

[Colin Cina]

Posted on July 11, 2018 at 15:04

Hi all, I have a similar issue with a F7 series. My UVC device driver crashes when trying to perform a USB OUT transfer involving a Data stage, thus using the DMA. It used to work before I integrated RTOS into this project. But now I get that AHBERR.

Did you figure it out? 

Chrisi, what do you mean with those RAM areas ? 

Kind regards

Colin Cina

[Tesla DeLorean]

Posted on July 11, 2018 at 17:38

People from 5 years ago, and two forum iterations are unlikely to get pinged via email, or respond.

On the F4 the CCMRAM at 0x10000000 can't be used for DMA, it's not supported via the bus matrix.

The F7 is going to be different, based on it's bus matrix (what will route where), and there are caching considerations.