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STM32C0- CMSIS- IRQn_Type

bym
Associate II

Hello everyone,

 

I'm a newbie working with STM32C031, setting up interrupt for user button (blue button) integrated on the board.

I am using VS Code, GNU_ARM_GCC, and CMSIS. No hal.

while setting up interrupts, interrupt priority, etc. , I am making use of CMSIS functions which use parameter IRQn_Type which defines interrupt numbers and defined interrupt number 4-15 as 7, which I do not understand.

Why 7?

How does shifting a "one" 7 to the left turn on interrupt 13, for example?

 

/**
  \brief   Enable Interrupt
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    __COMPILER_BARRIER();
    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    __COMPILER_BARRIER();
  }
}

typedef enum
{
/******  Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
  SVC_IRQn                    = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
/******  STM32C0xxxx specific Interrupt Numbers ****************************************************************/
  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
  RTC_IRQn                    = 2,      /*!< RTC interrupt through the EXTI line 19 & 21                       */
  FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                            */
  RCC_IRQn                    = 4,      /*!< RCC global Interrupt                                              */
  EXTI0_1_IRQn                = 5,      /*!< EXTI 0 and 1 Interrupts                                           */
  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                      */
  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                      */
  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                          */
  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                           */
  DMAMUX1_IRQn                = 11,     /*!< DMAMUX Interrupts                                                 */
  ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                                   */
  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts            */
  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                    */
  TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                             */
  TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                            */
  TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                            */
  TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                            */
  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt  (combined with EXTI 23)                           */
  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                                    */
  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                                  */
  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                                  */
} IRQn_Type;

 

1 ACCEPTED SOLUTION

Accepted Solutions
TDK
Guru

EXTI4_15_IRQn is interrupt 7. The ISER register has one bit per interrupt. Shifting "1" to the left by 7 places yields a 1 at the 7th bit and 0 everywhere else, which is the mask needed to enable EXTI4_15_IRQn.

 

The EXTI4_15_IRQn interrupt is common for pin numbers 4-15. They all come through on this same interrupt.

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View solution in original post

3 REPLIES 3
TDK
Guru

EXTI4_15_IRQn is interrupt 7. The ISER register has one bit per interrupt. Shifting "1" to the left by 7 places yields a 1 at the 7th bit and 0 everywhere else, which is the mask needed to enable EXTI4_15_IRQn.

 

The EXTI4_15_IRQn interrupt is common for pin numbers 4-15. They all come through on this same interrupt.

If you feel a post has answered your question, please click "Accept as Solution".
bym
Associate II

Thank you TDK.

 

I missed that in the documentation. I'll have a look again to see where it says interrupts 4-15 are turned on by bit 7.

 

Thank you very much. 

You can find the vector table in the reference manual.

The documentation for the ISER register will be in ARM documentation, since that's part of the core.

TDK_0-1722477984534.png

 

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