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PWM DMA generation with variable period
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2023-09-26 06:28 PM
Hi all,
I am trying to generate a PWM signal with both variable pulse width and period. I think the HAL_TIM_Base_Start_DMA function can only generate it with variable pulse width but not variable period. I have checked the timer cookbook and found the corresponding document at CH5 (p.44). (https://www.st.com/resource/en/application_note/an4776-generalpurpose-timer-cookbook-for-stm32-microcontrollers-stmicroelectronics.pdf) However, I still fail to realize it after copying the code provided on p.55. The pulse generated is a repeatable pulse with ARR and CRR as predefined value, the aSRC_buffer seems not able to load into the register. Can anyone tell me why, or provide me a same code which could work? Thanks a lot.
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STM32CubeMX
9 REPLIES 9
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2023-09-27 04:22 AM
Which STM32?
Read out and check/post TIM and DMA registers content.
JW
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2023-09-28 08:31 PM
Unfortunately there is no such materials about my case. I am using the STM32G474 discovery kit and I have read both the reference manual and timer cookbook. They did tell me how to configure the registers, but think neither of them mentioned how to start the pulse. I have used debug mode and checked that both the TIM1 and DMA register have the appropriate value, but the pulse is just not right, the DMA data
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2023-09-28 08:33 PM
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
uint32_t pwmData[12];
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim1;
DMA_HandleTypeDef hdma_tim1_ch1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_DMA_Init(void);
static void MX_TIM1_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_TIM1_Init();
MX_DMA_Init();
/* USER CODE BEGIN 2 */
pwmData[0] = (uint32_t) 3399;
pwmData[1] = (uint32_t) 0;
pwmData[2] = (uint32_t) 1699;
pwmData[3] = (uint32_t) 8499;
pwmData[4] = (uint32_t) 0;
pwmData[5] = (uint32_t) 6799;
pwmData[6] = (uint32_t) 3399;
pwmData[7] = (uint32_t) 0;
pwmData[8] = (uint32_t) 1699;
pwmData[9] = (uint32_t) 0;
pwmData[10] = (uint32_t) 0;
pwmData[11] = (uint32_t) 0;
/* Configure the AHB1 peripheral clock enable register */
/* DMA clock 1 enable, bit 0 = 0x00000001 */
RCC->AHB1ENR = 0x00000101; /* Reset value is 0x000100 */
/* Configure the DMA */
/* Channel2 is selected as the DMA channel */
/* 12.6.1 */
/* DMA1_Channel2->ISR = DMA interrupt status register, no need configure */
/* 12.6.2 */
/* DMA1_Channel2->IFCR = DMA interrupt flag clear register, no need configure */
/* 12.6.3 */
/* Configure the DMA channel 2 configuration register */
/* Priority level is high, bits 13-12 = 10 = 0x00002000 */
/* Memory size is 32 bits, bits 11-10 = 10 = 0x00000800 */
/* Peripheral size is 32 bits, bits 9-8 = 10 = 0x00000200 */
/* Memory increment mode enable, data will be stored in different memory location, bit 7 = 1 = 0x00000080 */
/* Transfer direction is memory to peripheral, bit 4 = 1 = 0x00000010 */
/* Transfer complete interrupt enable, bit 1 = 0 = 0x00000002 */
/* 0x00002000 + 0x00000800 + 0x00000200 + 0x00000080 + 0x00000010 + 0x00000002 = 0x00002A92 */
DMA1_Channel2->CCR = 0x00002A92;
/* 12.6.4 */
/* Configure the DMA channel 2 number of data to transfer register */
/* Number of data to transfer = array size = 12 = 0x0000000C */
DMA1_Channel2->CNDTR = 0x0000000C;
/* 12.6.5 */
/* Configure the DMA channel 2 peripheral address register */
/* Peripheral address = base address of the peripheral data register from which the data will be read = TIM1_DMAR */
DMA1_Channel2->CPAR = 0x40012FE0;
/* Configure the DMA channel 2 memory address register */
/* Peripheral address = base address of the memory data register from which the data will be read */
DMA1_Channel2->CMAR = (uint32_t)&pwmData;
/* Configure the DMA channel 2 configuration register */
/* DMA1 channel2 enable, bit0 = 1, = 0x00000001 */
DMA1_Channel2->CCR |= 0x00000001;
/* Configure the timer */
/* 28.6.1 */
/* Configure the TIM1 control register 1 */
/* Clock division = 1, bits 9-8 = 0, no need configure */
/* Auto-reload preload disable, bit 7 = 0, no need configure */
/* Counter used as upcounter, bit 4 = 0, no need configure */
TIM1->CR1 = 0x0000;
/* 28.6.2 */
/* TIM1->CR2 = TIM1 control register 2, no need configure */
/* 28.6.3 */
/* TIM1->SMCR = TIM1 slave mode control register, no need configure */
/* 28.6.4 */
/* Configure the TIM1 DMA/interrupt enable register */
/* Capture/compare DMA request enable, bit 9 = 1 = 0x00000200 */
TIM1->DIER = 0x00000200;
/* 28.6.5 */
/* TIM1->SR = TIM1 status register, no need configure */
/* 28.6.6 */
/* The TIM1 event generation register should be configured at last after buffer data is loaded */
/* 28.6.8 */
/* Configure the capture/compare mode register 1 */
/* Direction of CC1 channel is defined as output, bits 1-0 = 00, no need configure */
/* PWM mode 1 is selected, bits 16, 6-4 = 0110 = 0x00000060 */
/* Preload register is enabled, bit 3 = 1 = 0x00000008 */
/* 0x00000060 + 0x00000008 = 0x00000068 */
TIM1->CCMR1 = 0x00000068;
/* 28.6.10 */
/* TIM1->CCMR2 = TIM1 capture/compare mode register 2, no need configure */
/* 28.6.11 */
/* The TIM1 capture/compare enable register should be configured at last to enable the OC1 signal output */
/* 28.6.12 */
/* TIM1->CNT = TIM1 counter, no need configure */
/* 28.6.13 */
/* Configure the TIM1 prescaler */
/* Prescaler value = 0 = 0x0000 */
TIM1->PSC = 0x0000;
/* 28.6.14 */
/* TIM1 auto-reload register will be updated by DMA channel, reset value == 0x0000FFFF */
TIM1->ARR = 0x0000FFFF;
/* 28.6.15 */
/* TIM1 repetition counter register will be updated by DMA channel, reset value = 0x0000 */
TIM1->RCR = 0x0000;
/* 28.6.16 */
/* TIM1 capture/compare register 1 will be updated by DMA channel, reset value = 0x00000000 */
TIM1->CCR1 = 0x00000FFF;
/* 28.6.17 */
/* TIM1->CCR2 = TIM1 capture/compare register 2, no need configure */
/* 28.6.18 */
/* TIM1->CCR2 = TIM1 capture/compare register 3, no need configure */
/* 28.6.19 */
/* TIM1->CCR2 = TIM1 capture/compare register 4, no need configure */
/* 28.6.20 */
/* The break and dead-time register should be configured at last to enable the main output*/
/* 28.6.21 */
/* TIM1->CCR5 = TIM1 capture/compare register 5, no need configure */
/* 28.6.22 */
/* TIM1->CCR6 = TIM1 capture/compare register 6, no need configure */
/* 28.6.23 */
/* TIM1->CCMR3 = TIM1 capture/compare register 3, no need configure */
/* 28.6.24 */
/* TIM1->DTR2 = TIM1 timer deadtime register 2, no need configure */
/* 28.6.25 */
/* TIM1->ECR = TIM1 timer encoder control register, no need configure */
/* 28.6.26 */
/* TIM1->TISEL = TIM1 timer input selection register, no need configure */
/* 28.6.27 */
/* TIM1->AF1 = TIM1 alternate function option register 1, no need configure */
/* 28.6.28 */
/* TIM1->AD2 = TIM1 alternate function option register 2, no need configure */
/* 28.6.29 */
/* Configure the TIM1 DMA control register */
/* DMA burst length (DBL): 3 transfers = 00010 for bits 12-8 = 0x00000200 */
/* DMA base address (DBA): data transfer to ARR (the 12th register) -> RCR -> CCR1 = 01011 for bits 4-0 = 0x0000000B */
/* 0x00000200 + 0x0000000B = 0x0000020B */
TIM1->DCR = 0x0000020B;
/* 28.6.30 */
/* TIM1->DMAR = TIM1 DMA address for full transfer, automatically controlled by DMA transfer, no need configure */
/* Initiate the pulse */
/* Configure the event generation register */
/* Reinitialize the counter and generates an update for the register, bit 0 = 1 = 0x0001 */
/* Load data from buffer registers into preload registers */
TIM1->EGR = 0x0001;
/* Wait until the hardware automatically reset the update generation bit */
while(TIM1->EGR == 0x0001) {}
/* Load data from preload registers to update registers */
TIM1->EGR = 0x0001;
/* Configure the TIM1 break and dead-time register */
/* Main output enable, bit 15 = 1 = 0x00008000 */
TIM1->BDTR |= 0x00008000 ;
/* Configure the TIMx capture/compare enable register */
/* OC1 signal output enable, level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits, bit 0 = 1 = 0x00000001 */
TIM1->CCER |= 0x00000001;
/* Configure the TIM1 control register 1 */
/* Counter enable, bit 0 = 1 = 0x0001 */
TIM1->CR1 |= 0x0001;
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
RCC_OscInitStruct.PLL.PLLN = 85;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief TIM1 Initialization Function
* @PAram None
* @retval None
*/
static void MX_TIM1_Init(void)
{
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
htim1.Init.Prescaler = 0;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 65535;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = 0;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
sBreakDeadTimeConfig.DeadTime = 0;
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
sBreakDeadTimeConfig.BreakFilter = 0;
sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
sBreakDeadTimeConfig.Break2Filter = 0;
sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
}
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
/* DMA controller clock enable */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
__HAL_RCC_DMA1_CLK_ENABLE();
/* DMA interrupt init */
/* DMA1_Channel2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
}
/**
* @brief GPIO Initialization Function
* @PAram None
* @retval None
*/
static void MX_GPIO_Init(void)
{
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @PAram file: pointer to the source file name
* @PAram line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
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2023-09-28 08:34 PM
This is my code to generate 3 arbitrary pulse with different wavelength and period.
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2023-09-28 09:36 PM
PWM without DMA works?
JW
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2023-10-02 06:00 PM
Yep, I think so. This is because I can see a continuous pulse with predefined ARR and CCR value through the oscilloscope. However, the ARR and CCR value does not seems to updated by the DMA, and the pulse will not stop either
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2023-10-03 01:40 AM
Read out and check/post TIM and DMA registers content.
JW
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2023-10-03 06:33 PM
I am not sure which part has problem though. I have read the whole TIM and DMA register content, and apparently they are correct (I checked in a debug mode and compared with a HAL function which can generate the pulse successfully but can only edit one register instead of 3 that I am trying to do). But I think the value in debug mode matches except some setup about some setup in the BDTR (I still enabled it, just setting difference). But other than that, I think the other register in DMA and TIM register have been written correctly. Therefore, I think it might be problems in other part.
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2023-10-04 12:53 AM
Show. More eyes see more.
Ah, this is 'G4. So show DMAMUX, too.
I don't have a 'G4 at hand to try, but I wouldn't be surprised if it would require Update DMA for the DMAR/DCR mechanism to work.
JW
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