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Project feasible (DMA-I2S-SPI-SDIO)?

Associate II


I was wondering if I can get some feedback on the following project, mainly if the requirements I have are feasible?

I was thinking on using an STM32F4 or STM32F7.


The project consist of the following parts:

  1. An external DAC that is controlled through I2S by the MCU. Data will be read from the memory of the MCU and played by the DAC. The sample rate is 48 kHz, 32 or 24 bit. DMA will be used to send data to the DAC through the I2S interface.
  2. Concurrently, an external ADC will be read out by the MCU through SPI (also using DMA). The ADC will be a 24 bit ADC with 8 channels, read out at a sample rate of 16 kHz. 400 ms of data will be gathered at a time, resulting in `8 ch * 32 bit (I assume the DMA will use 32 bit instead of 24 bit?) * 16000 samples / sec * 400 ms` = 1638 kbit. The datarate will thus be 4096 kbit/s. There are several options to where the data will could be written:
    1. Data written to external memory. Possibly an SD card with SDIO. Could this be achieved through DMA (adc--spi over dma-->mcu--sdio over dma-->SD card)?
    2. Data written to a large, internal RAM buffer. This RAM buffer will be 1638kb = ~205kB.
    3. Data written to another external controller through SPI, similar to 2a.


I am not looking for an implementation, just a feel if this is possible to create (seeing the 'high' data/sample rates) on an STM32F4 or STM32F7, since I don't have experience with DMA.



Senior III

Depends on ADC, what part number? There are ADC with  8 data lines kind of octo-SPI, I don't think any F7 or F4 could handle those. Regarding DMA, rought estimation of troughoutput about 10-14 megawords (32-bits), about x4 times higher than required.

Depends a lot on the card, and the ability to write large media and file system aligned blocks of data. ie Clusters or Erase Block, 32 KB perhaps a good mix of size and alignment. Alignment of the file pointer being most critical in reducing unnecessary busy work and card interactions.

Several MB/s should be within reach on most platforms.

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Hi MasterT,

Thanks for your reply!

No ADC part has been selected yet, but I assume it would use normal SPI.
From your reply it sounds that using DMA will work for this set-up. Time to get my hands dirty and test this :-).

Hi Tesla DeLorean,

Thanks for your reply!

I haven't dug too deep into this yet, but several MB/s sound good. Guess now it is time to test this :-).