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Minimizing SCLK pulse time on SPI with STM32H745

dplogiic
Associate II

Hello STM community,

I'm working on optimizing SPI communication on an STM device, and I'm encountering an issue with the timing of SCLK pulses. After transmitting 16 SCLK pulses, there's a delay of 3μs before the next set of 16 pulses can be generated.

I need to reduce this delay to ensure that SCLK can be immediately generated after CS goes low. Can anyone suggest methods or configurations to minimize this delay and maintain a continuous SCLK stream after CS is pulled low?

I'm trying to achieve sampling rate for ADC ADS7046 interfacing.

sclk take same time even not used CS.

I want to sclk immediately on after cs low.

Below I attach some snap of spi cycle.

dplogiic_0-1713792741909.png

dplogiic_1-1713792774343.pngdplogiic_2-1713792788831.pngdplogiic_3-1713792800189.png

 

dplogiic_4-1713792925306.png

 

13 REPLIES 13

Use DMA.

JW

Uwe Bonnes
Principal II

Start by using the FIFO.

Uwe Bonnes
Principal II

If you need the framing with CS, read the reference and understand how NSS can  be used to automaitcally generate the frame around a packet.

Hello Uwe Bonnes,

Thanks for reply. I also used DMA with normal mode then frame also same as above with additional delay. So then I am trying with circular DMA that time data not read as given. and SCLK generated continuous and cs not toggle. please can you provide one example code with stm32h745 SPI DMA. I want to achieve 3msps sampling rate for ADC ads7046. 

The timing above does not look like hardware NSS. When using hardware NSS the timing between NSS and clock and between transfers is set by SPI_CFG2_MIDI and MSSI. HAL will probably have a way to set hardware NSS and those values, adding however a level of obfuscation between the reference manual and theseetings needed by HAL

dplogiic
Associate II

yes Uwe Bonnes, can you please provide example code and setting what to do. and which mode i need to select normal or circular dma?

dplogiic_0-1713863114800.pngdplogiic_1-1713863277077.png

 

Uwe Bonnes
Principal II

I do not use HAL

it's ok. can you share it. any type of example you can share. 

now i used with hardware nss 

blue= sclk, red= nss

dplogiic_0-1713867972243.png

dplogiic_1-1713868013743.png

how can i minimize sclk time 

dplogiic_2-1713868120739.png

dplogiic_3-1713868160985.png

without buffer print it also take same time.