Is the ordering of simultaneous ADC interrupt HAL callbacks deterministic?

[norlesh]

Is the ordering of simultaneous ADC interrupts deterministic and how could I find the ordering? I am triggering two ADC sample and converts simultaneously from a single timer (gave up on using "multi ADC mode" ) and need to know when the second interrupt occurs so I know I am working with the same time step.

[norlesh]

Actually just occurred to me that since both data registers will be ready at the same time (due to my configuration) that I can just access both ADC results during first interrupt and ignore/disable the other, so there is that solved ... But heck still be interested in the answer to the original question if anyone knows.

[Tesla DeLorean]

I think most rational implementations with the ADC on STM32 parts use DMA, and you get an interrupt when your array is half and completely full. And that you have buffers deep enough to account for latency and other interrupts, so that you can process the data quicker than it is being generated.

The EOC from one ADC would cause you to read the CDR (Common Data Register) and pull all the samples across all the ADC from there.

[norlesh]

doing motor control and want everything as fresh as possible (sampling position at 270kHz to correct for position error in stepper motor microsteps as they happen) so filling a full buffer isn't something I'm looking for. As for the CDR I am yet to find any data in it! I have my timer triggering ADC1 which is set to Dual mode along with ADC2. From my break point inside the interrupt handler both ADC data registers are being refreshed but CDR reads zero always (Tried looking in ADC->CDR and ADC123_COMMON->CDR)