I came across a discrepancy between two ST documents regarding the behavior of an IWDG reset on STM32H5 devices, and I’d like clarification on what exactly is reset when an IWDG event occurs.
Document 1: UM3150 Rev 2 – STM32H5 Safety Manual, Table 9 (CPU_SM_6)
States that the IWDG reset may result in an "incomplete" local safe state — it only resets the CPU and does not guarantee that application software can bring the system to a final safe state. This implies that I/O and peripherals may not be reset.
- Document 2: RM0481 Rev 2 – STM32H562/63xx Reference Manual, Section 11.3.2
States that an IWDG event results in a system reset, and all registers (except RCC_RSR and Backup domain) are returned to their reset values, which implies that peripherals and I/O should also reset.
Can ST clarify this apparent contradiction? Does the IWDG event reset only the CPU (as per UM3150), or the entire system including I/Os and peripherals (as per RM0481)?
