Any chance for CMSIS headers to be consistent across families?

[freddie_chopin]

Posted on February 23, 2017 at 11:18

The consistency of CMSIS headers for different STM32 families is really terrible, which makes writing a multiplatform project a misery. The project I'm talking about is obviously my C++ RTOS ( 

http://distortos.org/

  ), and SOME OF the problems I'm facing (just the few I remember now) are:

1. FLASH_SR_RDERR is defined only for STM32F72 and STM32F73, so the define is not available when you use any other STM32F7, F0, F1 or F4 chip.
2. Any defines for FLASH->KEY are not available for STM32F7 and F4, while available for F0 and F1.
3. Headers for F0 and F7 define just GPIO_OTYPER_OT_x, headers for F4 have GPIO_OTYPER_OTx, GPIO_OTYPER_OT_x and the 'new' '..._Pos' and '..._Msk' defines. The same is true for IDR, ODR, BSRR, but not true for others (like OSPEEDR, PUPDR, ...).
4. All headers I've checked have FLASH_SR_SOP, while the manuals always lists that this should be '..._OPERR' (which is not defined in any header).
5. ...

I'm talking about the most recent versions of these packages (unless you uploaded new versions within last 2 weeks). You're generating all of that with a script, so why not just try to make ALL of the families consistent?

I've only checked F0, F1, F4 and F7, but I'm pretty sure that when I check other families, the situation will be much worse...

#cmsis #header-files

[freddie_chopin]

Here's another one, and this one really drives me crazy.

Any header for L0 or L4:

typedef struct
{
  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
} DMA_TypeDef;                                                                  
                                                                                
typedef struct                                                                  
{                                                                               
  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
} DMA_Request_TypeDef; 

Any header for F0 (which has CSELR, so e.g. F091):

typedef struct
{
  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
  uint32_t      RESERVED0[40];/*!< Reserved as declared by channel typedef                   0x08 - 0xA4          */
  __IO uint32_t CSELR;        /*!< Channel selection register,                               Address offset: 0xA8 */
} DMA_TypeDef;

Do note that the offsets are identical, so why make the lives of library writers so miserable by introducing such pointless differences?