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About the interrupt enablel/disable in 'FreeRTOS_LowPower_LPTIM'

diverger
Senior

In the ST's example about the use of LPT with RTOS (STM32Cube_FW_L4_V1.15.1\Projects\B-L475E-IOT01A\Applications\FreeRTOS\FreeRTOS_LowPower_LPTIM). In the function 'vPortSuppressTicksAndSleep()', the interrupt is disabled as below:

/* Enter a critical section but don't use the taskENTER_CRITICAL() method as
	that will mask interrupts that should exit sleep mode. */
	__asm volatile ( "cpsid i" );
	__asm volatile( "dsb" );
	__asm volatile( "isb" );

I'm a little confused by the comments and the code. Per freeRTOS's docs, the code here should disable the interrupt but left the interrupts which will bring the MCU out of sleep enabled. Apparently, the code above will disable all the interrupts. But the comment say it doesn't use 'taskENTER_CRITICAL()' because it will mask the interrupts will make MCU exiting sleep, right? Then who will disable more interrupts? 'taskENTER_CRITICAL()' or 'cpsid i'???????

1 REPLY 1
Piranha
Chief II

As typical with ST's brainless code monkeys - the comments are nonsense and the code is flawed.

FreeRTOS functions like taskENTER_CRITICAL() really mask interrupts only up to configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY priority level using BASEPRI register and that will prohibit those interrupts from waking up CPU. Also it cannot be used here because it doesn't mask all interrupts. ARM also have PRIMASK register which can be set/reset by CPS instruction and masks all interrupts, but doesn't prohibit CPU wake-up. Look here for a detailed wake-up conditions.

So it seems that ST's solution is the right one, but let's look at it closely. Using CPS instruction is the right thing, but it's written as an inline assembler code compatible only with GCC compiler and lacks compiler barrier. Those monkeys will never grasp those... But all of that is done correctly in the simple and cross platform __disable_irq()/__enable_irq() macros provided by ARM, which are also present in their own Cube packages... And neither DSB nor ISB is required after interrupt masking with CPS. The monkey didn't even knew the ARM software basics.