Nucleo H723ZG ADC Sampling Problem

[gnlcflx]

Hi

I'm trying to sample a sine wave between 400 and 500 kHz with the Nucleo H723ZG. I'm using the 16 bit adc 1 with following configuration:

• sampling rate: 2 MSps
• T_sampling: 16.5 clock cycles
• f_adc: 50 MHz (from PLL2P: 100 MHz)
• DMA circular mode
• continuous conversion mode
• adc trigger: regular conversion launched by software

I'm trying to calculate the correct frequency of the signal. The calculated frequency fluctuates between +-500Hz, which is not accurate enough.

The code to calculate the frequency has been tested with pre-generated values with a given frequency and works fine with an accuracy of +- 1Hz.

I already checked the reference voltage VREF, which is fine, and removed L1 (as described in https://community.st.com/t5/stm32-mcus-products/fluctuations-in-adc-value-of-stm32h743-mcu/m-p/331501#M79889).

There seems to be a problem with the sampling / sampling rate.

Any solutions will be highly appreciated .

Thank you

[MasterT]

500 Hz / 2 MHz ~= 10^-3, this is about what I'd expect from RC oscillator. Seems HCI is primary clock, try to change HSE in by-pass and feed 8.33 MHz out of ST-Link. You have to reconfigure ST_Link as well

[TDK]

How are you calculating the frequency?

Using an FFT with a peak estimation is going to give the highest accuracy.

Share some data with actual frequency and calculated frequency.

[gnlcflx]

Hi @MasterT 

Thanks for your answer. I allready use the HSE clock, which is from the ST-Link (8 MHz).

Is there maybe something else wrong with the clock configuration?

[gnlcflx]

@TDKthanks for your answer. I'm using an FFT and the goertzel algorithm to estimate the frequency. I did some frequency calculation on the microcontroller (1000 values):

The input frequency was generated with a signal generator (457 kHz) and checked with a spectrum analyzer. The accuracy of the generator is +- 2Hz.

As mentioned before: I checked the frequency calculation with pre-generated values and it works fine, also on the microcontroller.

[MasterT · Accepted solution]

Using 8 MHz from ST_Link has no sense, since ST-Link is running on it's own HCI in default config. You need to reprogram ST-Link to run on 25 MHz crystal clock , than divide by 3 - so strange 8.33 MHz output. My understanding that ST use 25 to comply with Ethernet 50 MHz requirements.

  It's not very convenient to re-map all frequencies, I usually set PLL to 950 MHz for my H743/753, but it's the easiest way to have clean primary clock on nucleo-H7. 

[gnlcflx]

@MasterTthank you very much for your help. I changed the ST-Link clock to the 25 MHz crystal oscillator and divided it by 5 (5 MHz). After changing the clock configuration in CubeMX, it worked perfectly fine!

[MasterT]

BS, there is no option divide by 5. 

[gnlcflx]

@MasterT 

Yes there is the option, I use the ST-Link upgrade version 3.16.8. Maybe it also depends on the nucleo board, I use the H723ZG...

[MasterT]

Ooooops, mea culpa. 

Thanks for reply, will update my software