Nucleo-F303RE want to set timer source muxes to use PLLCLK*2, to yield 2 * 72 MHz=144 MHz resolution

[ericfont]

I'm on Nucleo-F303RE board, which according to the page 129-130 of the reference manual (RM0316 Rev 10) I should be able to set "TIMx (x = 1/2/3/4/8/15/16/17/20) can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively":

However, when I create a new project for Nucleo-F303RE board, and configure the clock tree to meet these conditions (system clock source is the PLL && AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively), then I can't seem to toggle the dot in the muxes for TIMx source mux (where x=1, 8, 15, 16, 17, 2, 3/4), and the dots in the muxes are greyed out int he clock configuration tool:

I'm new to STM32 environment, so I might be doing something basic wrong.

[AScha.3 · Accepted solution]

As long as you have nothing enabled/used , that uses a certain clock mux out , its not activated...grey.

Select -maybe- TIM1 and then choose the clock for it - mux is no more grey then !

[ericfont]

Aha! Enabling the timer first successfully ungreyed the mux so I could change the configuration dot to select PLLCLK*2=144 MHz. Thanks!

[Tesla DeLorean]

Can't say I'd ever noticed this feature, but not a user of the F3's

Generally on other STM32 the PLL VCO pulses at a higher frequency and is always divided by two to get a square wave (50/50 duty) as the CPU core is built on that expectation.