[Layout] Ground plane recommendation for STM32 on BMS board

[ytshin0877]

 

Context (brief):

• Board: BMS that charges/discharges cells at 1–2 A

• MCU: STM32G474RET6 using HSI, 3× ADC, 1× DAC, USB FS (D+, D−), a few GPIOs.

• Constraint: Battery sense node carries an unavoidable ~20 MHz component from an external stim source (cannot eliminate at source).

• Goal: Accurate voltage sensing while keeping digital/USB activity and power-stage di/dt from polluting ADC/DAC/reference.

What I need advice on (grounding only):

1. Single solid plane vs split AGND/DGND:

   • For STM32 with VSSA/VDDA and VSS/VDD, is the consensus to use one continuous GND plane (no hard moat) with functional partitioning—or do you still recommend a true AGND/DGND split in this use case (1–2 A BMS + ~20 MHz on the measured node)?

   • If “single plane,” where do you prefer the AGND focus/tie—directly under/next to VSSA/VREF+ (shortest loop) versus a separate star just for the analog front end?

2. If I were to have two separte ground plane

   1. What component should I connect to AGND, and DGND?: My assumption was that since BMS board ground has lots of current(Charging/Discharging current flowing+ 20MHz signal), I wanted to separte ground for ADC and all the peripherals for the MCU. 
   2. Could you recommend the best strategy for implementing this MCU collaborated and implmented in the one PCB together?

Thank you in advance 

I would really appreciate any help regarding this layout recommendation

[Igor Cesko]

Hello ytshin0877,

The ground design: one question is the analog accuracy and next is the EMC robustness.

For high analog accuracy is the best to have separated grounds and connect then in one point (star topology). But then there can be less EMC robustness due to higher impedance between analog and digital grounds (high  frequency currents can cause higher difference between grounds).

For EMC robustness is good to have one strong ground plane. But then some high currents can flow through analog signal path (causing voltage drop on given impedance). The goal in this type of design is to minimize currents flowing through analog signal path. The ground impedance is quite low (because one robust GND plane) but we must suppress the current flowing through analog path. This can be achieved by correct component placement on the board: the high current part must not flow through analog signal path. Sometimes we can insert on PCB tiny isolation paths in the GND plane - to regulate the high current flow to some direction on the GND plane.

Currents in your design are higher (and high frequency) and there is high frequency disturbance: 20MHz signal. I suggest to use one GND plane according to above suggestions for more EMC robustness and optimize the component placement on PCB.

  Regards

                             Igor