Issue with memory sharing between cores

[Karthick008]

Hi Team, I'm new to STM32H7 controller. I've started exploring the shared memory in this dual core controller. I found a great one from MAJERLE. Thanks for that. I used the same concept and made a Flag to check for new data to read and write, it was working okay.  But, the time gap between write to read was so huge. I'm not getting why it's so. Then, I tried to poll the while(1) loop by toggling GPIO, to see how frequently it is polling the flag, but I found that the while(1) loop itself running very slow, unable to figure out what causing it slow. Please, guide me to resolve this issue. My requirement is that, I'm trying to share the some amount of data between M4 and M7  at very fast frequency. Suggest the best way to handle this problem.
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common.h

/* Buffer from CM4 to CM7 */

#define BUFF_CM4_TO_CM7_ADDR MEM_ALIGN(SHD_RAM_START_ADDR)

#define BUFF_CM4_TO_CM7_LEN MEM_ALIGN(sizeof(ringbuff_t))

#define BUFFDATA_CM4_TO_CM7_ADDR MEM_ALIGN(BUFF_CM4_TO_CM7_ADDR + BUFF_CM4_TO_CM7_LEN)

#define BUFFDATA_CM4_TO_CM7_LEN MEM_ALIGN(0x00000400)

typedef struct ringbuff {

#if RINGBUFF_USE_MAGIC

uint32_t magic1; /*!< Magic 1 word */

#endif /* RINGBUFF_USE_MAGIC */

uint8_t* buff; /*!< Pointer to buffer data.

Buffer is considered initialized when `buff != NULL` and `size > 0` */

size_t size; /*!< Size of buffer data. Size of actual buffer is `1` byte less than value holds */

size_t r; /*!< Next read pointer. Buffer is considered empty when `r == w` and full when `w == r - 1` */

size_t w; /*!< Next write pointer. Buffer is considered empty when `r == w` and full when `w == r - 1` */

ringbuff_evt_fn evt_fn; /*!< Pointer to event callback function */

#if RINGBUFF_USE_MAGIC

uint32_t magic2; /*!< Magic 2 word */

#endif /* RINGBUFF_USE_MAGIC */

volatile uint8_t flag;

} ringbuff_t;

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M7 Codes:

Linker files:

MEMORY

{

RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K

FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */

DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K

RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K

ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K

RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = RAM_D3_SIZE

}

.shared :

{

_sshared = .;

*(.shared);

_eshared = .;

} > RAM_D3

ASSERT((_eshared - _sshared) <= RAM_D3_SIZE, "RAM D3 too big")

main.c:

volatile ringbuff_t* Vaddr = (ringbuff_t*)rb_cm4_to_cm7;

while(1)

{

if(Vaddr->flag == 1)

{

__DSB();

memcpy(addr, Vaddr->buff, 100);

__DSB();

Vaddr->flag = 0;

}


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M4 Code:

Linker file:

MEMORY

{

FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K

RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K

RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = RAM_D3_SIZE

}

.shared :

{

_sshared = .;

*(.shared);

_eshared = .;

} > RAM_D3

ASSERT((_eshared - _sshared) <= RAM_D3_SIZE, "RAM D3 too big")

main.c :

volatile ringbuff_t *Vaddr = (ringbuff_t*)rb_cm4_to_cm7;

while(1){

if(Vaddr->flag == 0)

{

memcpy(&Vaddr->buff[0], &numbers, 100);

__DSB();

Vaddr->flag = 1;

}

}

IMG1:

The above image shows the Write and Read durations. Yellow is the Write duration, after Write finishes it's job,

then Green signal goes High, which shows the read duration.

There's a time gap between these two operations, which is very huge.

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IMG2:

 The above image shows, a GPIO toggle inside while(1) loop. Here the Yellow signal represent GPIO toggle

inside M4 core, and Green signal shows GPIO toggle inside M7 core.

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