2021-03-16 12:52 AM
2021-03-16 01:42 AM
Hello
Yes, there are impacts when work on 1.8v
Increased flash wait states, reduced ADC sampling rates, reduced max clock output frequency on I/O pins, reduced max voltage for five volt tolerant pins and others .
Suggest to read carefully the Datasheet before decide to reduce the voltage.
2021-03-16 01:42 AM
Hello
Yes, there are impacts when work on 1.8v
Increased flash wait states, reduced ADC sampling rates, reduced max clock output frequency on I/O pins, reduced max voltage for five volt tolerant pins and others .
Suggest to read carefully the Datasheet before decide to reduce the voltage.
2021-03-16 01:46 AM
Thank you for your reply.
2021-04-05 05:04 AM
Hello Vangelis Fortounas,
I am trying to validate digital interfaces like SPI, I2C with STM32 VDD: 1.8V. But I am facing an issue with STM JTAG as it is working @3.3V.
Even I tried with Level translator but not able to make it work. Which STM JTAG you used while working with VDD: 1.8V?
Thank you,
Abhi
2021-04-05 06:16 AM
The authentic ST-LINK/V2 pods are supposed to work down to 1.65V, with VTarget provided to it's buffers via Pin 1 or 2 of the standard 20-pin header. https://www.st.com/en/development-tools/st-link-v2.html
Consider if the L4+ parts are more appropriate for a redesign, the whole GPIOG bank can be powered from its own VDDIO supply
2021-04-06 02:20 AM
Hello
STLINK-V3SET with B-STLINK-ISOL board is also capable to work with stm32 targets working down to 1.65V.