I've been working with the STM32H7B3LIH6Q board on Segger, and it was functioning normally until I happened to flash the code below to it. Now I get "no idcode detected" on Segger and "No debug probe detected" on STM32CubeProgrammer when connected to ST-Link. In fact, connecting the ST-Link module doesn't even power the board. I made sure the correct power pins were shorted too. I then tried changing the on-board switch (aka boot0) to 1:sys-mem and power cycling several times but I still couldn't connect. The JLinkSTM32 utility doesn't seem to work either and some of the other utilities also seem to be unable to connect.
Is there any way to reset the option bytes or flash memory? Maybe using JLinkExe to enter direct commands? I feel like I've almost tried everything and it seems somewhat ridiculous to me that a board would be so poorly designed that setting the clock frequency too high in software (I didn't realize 400 MHz was too high) would irretrievably brick it, if that's what happened.
At the very least, is there anything wrong with this code besides the the sys_clk frequency being set to 400 MHz? Is that a major problem? I really don't want to cause another board to go the same route.
RCC -> CFGR &= 0; // Reset register
int32_t cfgr = RCC -> CFGR;
int32_t sws_pll1 = RCC_CFGR_SWS_PLL1;
int32_t status = cfgr & sws_pll1;
while (!status) {
cfgr = RCC -> CFGR;
sws_pll1 = RCC_CFGR_SWS_PLL1;
status = cfgr & sws_pll1;
} // System clock switch status: Wait until PLL1 is system clock; TODO: hangs*/
// RCC source control register
RCC->CR |= RCC_CR_HSION; // HSI clock enable
while (!(RCC->CR & RCC_CR_HSIRDY)); // Wait until HSI clock is ready
/* -------- PLL Config -------- */
// RCC PLLs clock source selection register
RCC -> PLLCKSELR |= RCC_PLLCKSELR_PLLSRC_HSI; // Select HSI as PLL clock source (hsi_ck)
// Note: Must have PLL1ON = 0 for modifying prescaler
RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1; // Reset prescaler for PLL1 to disabled
RCC -> PLLCKSELR |= RCC_PLLCKSELR_DIVM1_5; // Set prescaler for PLL1 to divsion by 32
// RCC PLL1 fractional divider register
RCC -> PLL1FRACR = 0; // Set FRACN to 0
// RCC PLLs configuration register
RCC -> PLLCFGR |= RCC_PLLCFGR_PLL1FRACEN; // PLL1 franctional latch enable
RCC -> PLLCFGR &= ~RCC_PLLCFGR_PLL1VCOSEL; // Select PLL1 output frequency range: wide VCO range from 128 to 560 MHz
RCC -> PLLCFGR |= RCC_PLLCFGR_PLL1RGE_3; // Select PLL1 input reference frequency range: between 8 and 16 MHz
// Note: Must have PLL1ON = 0 and PLL1RDY = 0 for enabling divider output
RCC -> PLLCFGR |= RCC_PLLCFGR_DIVP1EN; // PLL1 DIVP divider output enable
RCC -> PLLCFGR |= RCC_PLLCFGR_DIVQ1EN; // PLL1 DIVQ divider output enable
RCC -> PLLCFGR |= RCC_PLLCFGR_DIVR1EN; // PLL1 DIVR divider output enable
// RCC PLL1 dividers configuration register
// Note: Must have PLL1ON = 0 and PLL1RDY = 0 for writing bits
RCC -> PLL1DIVR &= 0; // Reset register
RCC -> PLL1DIVR |= (0x18F << RCC_PLL1DIVR_N1_Pos) & RCC_PLL1DIVR_N1; // DIVN = 0x18F = 399
RCC -> PLL1DIVR |= (0x1 << RCC_PLL1DIVR_P1_Pos) & RCC_PLL1DIVR_P1; // DIVP = 1
RCC -> PLL1DIVR |= (0x1 << RCC_PLL1DIVR_Q1_Pos) & RCC_PLL1DIVR_Q1; // DIVQ = 1
RCC -> PLL1DIVR |= (0x1 << RCC_PLL1DIVR_R1_Pos) & RCC_PLL1DIVR_R1; // DIVR = 1
// RCC source control register
RCC -> CR |= RCC_CR_PLL1ON; // PLL1 enable
//while((RCC -> CR & RCC_CR_PLL1RDY) == 0); // Wait until PLL1 clock is ready; TODO: hangs
