ADC + DMA on STM32H753ZI

[eskilru]

Hi All,

I have a question regarding the validity of my implementation of ADC + DMA on the STM32H753ZI.

I had quite a lot of trouble getting the HAL_ADC_ConvCpltCallback configured as

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
  {
    counter ++;
    BSP_LED_Toggle(LED_RED);
  }

to trigger, as all other guides did not work until I found this guide: https://www.youtube.com/watch?v=_K3GvQkyarg

Where at around 27 minutes there is shown how how to enable the MPU and then how to configure DMA around it.

For me the DMA callback did not trigger at all until I :

- Disabled Speculation default mode and enabled CPU ICache and DCache

- Enabled MPU region 0, setting the base address to 0x38000000 using RAM_D3, all access permitted and disabling

MPU Instruction Access, Sharebility permission, Cacheable Permission and Bufferable Permission.

- Added a RAM modification in STM32H7XX_FLASH.id as

/* RAM MODIFICATION */
  .nocache(NOLOAD) :
  {
    . = ALIGN(32);
    * (.nocache)
  } > RAM_D3

and then setting my DMA buffer as:

volatile uint16_t adcData[ADC_NUM_CONVERSIONS] __attribute__((section(".nocache")));;

Only after this did the DMA work in Circular mode with the ADC, triggering the callbacks. I must admit I don't fully

understand all the changes that had to be made, and so I am worried that it might not be set up correctly.

I have looked trough all the examples I could find and the DMA documentation for the

STM32H753 (although I am a bit blind at times), but I could not find anything related to a requirement for the MPU

to be enabled like this for DMA to work. My question is then whether this is the correct configuration, as there is not

much documentation for the STM32H753ZI specifically.

I hope it is okay to ask for this:)

[Saket_Om]

Hello @eskilru 

The MPU is not strictly required for DMA operation. However, if you enable the CPU cache (which is highly recommended for performance), and your DMA buffers reside in cacheable memory, you must manually manage cache coherency by invalidating or cleaning cache lines before and after DMA transfers.

Please refer to these materials below for more information about MPU setting and cache:

Level 1 cache on STM32F7 Series and STM32H7 Series

STM32 MPU tips - 1 MPU usage in STM32 with ARM Cortex M7 - YouTube