ST25R3916b collision resolution not working, NFC-A & NFC-V tags not working/detected

[marcklp]

Hello,

I am currently working as a student on designing my own hardware for reading and writing NFC tags. Although I lack experience in RF design, I have completed the electronic design and antenna matching process. My setup includes an STM32U575RGTx microcontroller connected to an ST25R3916B NFC chip via SPI. The antenna, sourced from Taoglas, is connected to the matching circuit, and I have confirmed the RF field using a spectrum analyzer.

This project does not utilize the STM HAL; instead, I am working in bare metal. I have developed a HAL for SPI communication, which is functioning without errors. Additionally, I have ported the RFAL library to my project to facilitate interaction with the NFC chip.

At present, I have two types of tags for testing: NFC-A T2T and NFC-V tags. I have enabled the necessary configuration in rfal_platform.h and implemented the example from the X-NUCLEO-NFC08A1 to attempt reading the tags.

However, I am encountering issues. When I try to read the NFC-A tag, the process does not progress past RFAL_NFC_STATE_POLL_COLAVOIDANCE in the rfalWorker() function, and gNfcDev.devCnt remains at 0. In contrast, when I attempt to read the NFC-V tag, the state does not reach RFAL_NFC_STATE_POLL_COLAVOIDANCE; instead, it stays in RFAL_NFC_STATE_POLL_TECHDETECT and fails to detect any tags.

I have a logic analyzer connected to my SPI and IRQ pins and can provide traces if needed.

Do you have any insights into where my error might be?

Thank you in advance for your assistance.

Best regards,
Marc

[Brian TIDAL]

Hi,

can you first enable ST25R_SELFTEST and ST25R_SELFTEST_TIMER compilation switch to make sure interrupt handling and timer management is correct?

Then can you connect your logic analyzer on SPI (CLK, MISO; MOSI and CS) + ST25R3916_INT and provide us the log file?

Can you also confirm you have followed the application note AN5276 in particular the design verification chapter?

Rgds

BT

[marcklp]

Hi Brian,

ST25R_SELFTEST and ST25R_SELFTEST_TIMER is defined and is working without errors.

I have not followed the application note in the design verification chapter, because i dont have the ISO calibration coil.

I have now tried a measurement with a VNA of the matching circuit with antenna. My VNA is connected at RFO1 and RFO2 directly at the ST25R3916b, driver output resistance is set to high Z. I have attached a screenshot of the measurement.

I am using FXC.35.52.0075X.A.dg antenna from Taoglas, matched with the ST25 Antenna matching tool to a target Z of 20 Ohm and Q of 20. 

Best regards,

Marc

[Brian TIDAL]

one question from RF expert: can you share antenna parameter and matching component values you used and how you came to those values?

Rgds

BT

[marcklp]

Hi Brian,

thanks for asking your RF experts.

I had a look at my circuit and found some capacitors which did not have the same values as i originally planed. I replaced them and now i have definitely improved the RF Field. I have attached a screenshot of the new measurement with antenna tuning.

Here are the values for the generation i used:

inductance: 1070nH

DC resistance: 1650 mOhm

Parallel resistance: 3040 Ohm

Self resonance: 75.4MHz

EMC inductor: 270nH

DC resistance: 500mOhm

EMC filter: 11750 kHz

Targets: Z 20Ohm, Q 20

In the calculated result in the antenna matching tool, i used 33pF capacitors instead of 36/37 pF. I also replaced the 0.87 Ohm resistors before the antenna with 0 Ohm.

I used AAT to tune the antenna instead of manually tuning the caps mayself. I still have a imaginary value of 15.72 Ohm. Which capacitors do i have to change to reduce this ? Should i manually try to tune the capacitors instead of using AAT?

Thanks in advance.

Best regards,

Marc

[Blake_Victor]

Hi,

After importing the antenna parameters (values you provided), the impedance chart you get doesn't match the simulation output, which still needs fine-tuning.

Reason: You might have misplaced the components or used different values. Please re-check the components you have placed on the board, and you can fine-tune the impedance.

If you provide us with more details, such as:

• The evaluation board you are using
• The antenna model

A picture of your setup would also be helpful for debugging.

Here, I am including the simulation results with the values you provided.

Regards,

BV

[marcklp]

Hi,

Currently, I am utilizing the antenna for which I provided the parameters earlier. After running your simulation, I replaced the components on the board accordingly. However, I encountered an issue with the tuning capacitors connected to AAT_A. They have a tuning range of 100pF to 200pF, but my new calculations indicate that I need to tune them to 67pF, which is unfortunately not feasible with the components I have on hand.

As a workaround, I decided to remove the tuning capacitors from the circuit entirely and replaced them with a single capacitor. Originally, from the simulation I had a 36pF capacitor in parallel with the tuning capacitor, which needed to be adjusted to 67pF. Instead, I have now used a 100pF capacitor in that position. The updated circuit can be seen in rfCircuit2.png.

I have also attached the measurement results with the new set of capacitors. However, it appears that the results are still significantly different from the simulation. Additionally, I included a picture of the PCB, highlighting the points where I connected the VNA and the antenna.

For your reference, the antenna is intended to be connected at the bottom via a JST connector. To bypass the board, I connected them directly to the 1Ω capacitors.

Antenna: FXC.35.52.0075X.A.dg
Board: Self-designed PCB with STM32U575RG as the MCU

Thank you for your assistance, and I look forward to your insights.

Best regards,
Marc

[Blake_Victor]

Hi,

Thank you for the information you have provided.

After reviewing it, I noticed that the capacitor package size highlighted in yellow is different from the others. Could you please explain the reason for using a different package size for these capacitors? Larger capacitors may have slightly higher parasitic inductance compared to smaller capacitors, which can affect the impedance at high frequencies. Additionally, I noticed that you have added a tuning capacitor (C126) in the schematic, which is missing in the prototype.

Potential reasons for the discrepancy between the results might be:

• Parasitic capacitance that is often not accounted for in simulations.
• Incorrect calibration of measurement equipment (VNA).

Possible solutions you may try:

• Optimize the PCB layout, ensuring proper grounding.
• Include parasitic capacitance in your simulation model.
• Calibrate your network analyzer before taking measurements.
• Use low tolerance capacitors.

Best regards,

Blake

[marcklp]

Hi Blake,

it was not my intention to use a larger package for the capacitor. As a student in information technology, this was my first experience with hardware design. My primary focus was on the schematic, while a colleague managed the layout. I likely selected the 0805 package by mistake and did not notice the discrepancy.I did ensure that all the necessary layout recommendations for the NFC design from your application note were forwarded to him. I have reviewed all the capacitors used in the design, and they all have a tolerance of 5%. Do you think this is sufficient, or should I consider upgrading to 1% tolerance for my redesign?

The tuning capacitor C126 is not missing from the design; it was inadvertently obscured due to my inadequate labeling in the previous screenshot. To clarify, I have attached an image of the layout design. 

To verify my Vector Network Analyzer (VNA), I purchased a STEVAL-25R3916B and connected my VNA to it. The measurements I obtained look excellent, as expected. I have attached the measurement results.

My next step will be to calculate the parasitic capacitance of the PCB circuit and incorporate it into the simulation in Qucs.

Best regards,

Marc

[marcklp]

there are the attachments i forgot