2018-08-27 05:37 PM
Edit: I solved the problem, it was my own fault! The Operation Control Register's bit 7 was set to 0 when it should have been set to 0. Thanks!
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Hello all,
I am working with the ST25R3911B discovery board (ST25R3911B-DISCO) and am attempting to directly interface the ST25R3911B IC with an Atmel microcontroller (in this case, and Arduino Uno).
Over SPI, I can read and write the registers of the ST25R3911B with no issues, I can even send direct commands. The ST25R3911B reacts/responds to my actions as I would expect it to.
The issue I have ran into is that I am simply unable to read or write to the FIFO. This is confusing because, in principle, it is a very similar operation to reading/writing the register. The only difference to the microcontroller is that the Mode Bits and 'trailer' it transmits are different. Refer to page 33 of the ST25R3911B to take a look at that detail.
After trying to write to the FIFO, the 'FIFO Status Register 1' (refer to page 97) does not change; it always reads zero. This indicates that I did not actually write anything to the FIFO.
Further, after trying to read the FIFO, bit 6 of the 'FIFO Status Register 2' does not change (nor does bit 5, not that it should though). This indicates that no data was actually read from the FIFO.
So I can't read or write to the FIFO, but registers and direct commands are fine. Due to this, I don't think my problem involves my SPI settings or my microcontroller.
I think it could be two things:
Any ideas what might be behind this?
Thanks much,
Simon R.
Solved! Go to Solution.
2018-08-31 02:42 AM
Hi Simon,
If you use the direct command Write FIFO with a certain number of bytes this will be reflected on the fifo_b bits (FIFO Status Register).
The other bits you mentioned fifo_unf and fifo_ovr, will only be affected when the FIFO underflows/overflows during transmission/reception.
To verify your communications you should be able to write to the FIFO n bytes, check the FIFO Status register, and then retrieve the same bytes with a Read FIFO command.
From your description it seems a SPI issue. Please verify the SPI signals and check that the Chip Select line is OK.
Perhaps if you add a SPI trace we can better support you.
Kind regards
GP
2018-08-31 02:42 AM
Hi Simon,
If you use the direct command Write FIFO with a certain number of bytes this will be reflected on the fifo_b bits (FIFO Status Register).
The other bits you mentioned fifo_unf and fifo_ovr, will only be affected when the FIFO underflows/overflows during transmission/reception.
To verify your communications you should be able to write to the FIFO n bytes, check the FIFO Status register, and then retrieve the same bytes with a Read FIFO command.
From your description it seems a SPI issue. Please verify the SPI signals and check that the Chip Select line is OK.
Perhaps if you add a SPI trace we can better support you.
Kind regards
GP
2019-01-03 12:54 AM
Hi all,
I have finally revisited this issue after a few months away from it, and I found the actual solution to my problem within five minutes of returning to it. It was painfully obvious: bit 7 ('en') of the the Operation Control Register must be set to 1. Now the FIFO can be read and written to as expected.
Thanks much!