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STSPIN840 EN/FAULT pin management

Minkyu Kim
Associate III

Hello,

I have some question about use STSPIN840.

0693W000005ArkRQAS.pngPage 19 in datasheet, R_EN and C_EN's value are 39KΩ and 10nF.

In the graph that is the basis of the recommended value, the value of V is 3.3V.

0693W000005ArkMQAS.pngAlso in page 18, FAULT and EN pins in MUC are tied Driver's EN/FAULT pin.

0693W000005ArkbQAC.pngAnd this typical schematic, each EN/FAULT pin's resistor is tied V_DD.

Do they have to be tied to 3.3V or is it okay to configure as shown in Figure 9?(In this case, VDD means the MCU's EN pin is 3.3V?)

A lot is difficult because it is the first time to design.

Best regards,

Minkyu Kim.​

1 ACCEPTED SOLUTION

Accepted Solutions
Dario CUCCHI
ST Employee

Hi Minkyu,

The REN and CEN are used to delay the turn on of the power bridge after a failure event.

The delay is determined by the REN and CEN time constant but also depends on the voltage applied on the RC network.

This is usually 3.3V because it is the most common voltage of the MCU.

In fact in figure 9 it is the level of EN_MCU pin ( so the supply of the MCU and its GPIO)

In the example of figure 14 it is depicted as an external VDD, but this is usually the same net supplying the MCU.

The topology in figure 9 allows to differentiate the functions:

  • one MCU pin (EN_MCU - output only) which enable or disable the power stage
  • another MCU pin (FAULT_MCU - input only) for the fault read-back

The example of figure 14 uses one pin, just considering that many MCU can configure their GPIO as open drain pin.

In this case you can set an interrupt on the falling edge of this pin to detect if a fault occurs.

And also you can drive the same pin low to disable the power stage or leave it in high impedance.

In this case the pin will be pulled up and, after the delay introduced by RC constant, enables the power stage.

So if you want to use only one GPIO of the MCU use figure 14 topology.

But if the MCU you are using cannot support open drain operation with interrupt or status readback, use figure 9 topology.

Then consider, if you are using both OUTA and OUTB you have to do it twice (one for EN/FAULTA and the other for EN/FAULTB).

If you have other questions let me know.

Have a good day !

View solution in original post

1 REPLY 1
Dario CUCCHI
ST Employee

Hi Minkyu,

The REN and CEN are used to delay the turn on of the power bridge after a failure event.

The delay is determined by the REN and CEN time constant but also depends on the voltage applied on the RC network.

This is usually 3.3V because it is the most common voltage of the MCU.

In fact in figure 9 it is the level of EN_MCU pin ( so the supply of the MCU and its GPIO)

In the example of figure 14 it is depicted as an external VDD, but this is usually the same net supplying the MCU.

The topology in figure 9 allows to differentiate the functions:

  • one MCU pin (EN_MCU - output only) which enable or disable the power stage
  • another MCU pin (FAULT_MCU - input only) for the fault read-back

The example of figure 14 uses one pin, just considering that many MCU can configure their GPIO as open drain pin.

In this case you can set an interrupt on the falling edge of this pin to detect if a fault occurs.

And also you can drive the same pin low to disable the power stage or leave it in high impedance.

In this case the pin will be pulled up and, after the delay introduced by RC constant, enables the power stage.

So if you want to use only one GPIO of the MCU use figure 14 topology.

But if the MCU you are using cannot support open drain operation with interrupt or status readback, use figure 9 topology.

Then consider, if you are using both OUTA and OUTB you have to do it twice (one for EN/FAULTA and the other for EN/FAULTB).

If you have other questions let me know.

Have a good day !