ST1S10 Frequency and Ripple- I have designed board for 900KHZ by Connecting Synch Pin to GND, But still i could get 980KHZ Frequency.. is this normal behavior.. also Frequency WF is not Square.. Ripple facing is 40mV (not acceptable for my controller)

Chiku · ‎2022-02-11

Peter BENSCH · ‎2022-02-14

The ST1S10 is a switching regulator with a free-running oscillator whose frequency accuracy cannot be compared to a crystal oscillator. In the datasheet, page 9 of the ST1S10, the frequency range is given when SYNC is connected to GND:

PWM fs - PWM switching frequency: min 0.7, typ 0.9, max 1.1 MHz.

This specification corresponds to a permissible deviation of ±200kHz, whereby your measured 980kHz are perfectly within the tolerance range.

Ripple: is typical to a greater or lesser extent in switching regulators by principle. However, you can minimise the ripple by following the instructions in the datasheet, e.g. using ceramic capacitors with low ESR and optimising the layout, see section 5.3.

Regards

/Peter

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Chiku · ‎2022-02-11

Ripple frequencY is 7.2KHZ

Can you help where is problem?

Peter BENSCH · ‎2022-02-14

Welcome, @Chiku, to the community!

If you connect SYNC to GND, the ST1S10 will indeed operate at 900kHz. What frequency did you expect?

What do you mean by WF?

Regards

/Peter

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Chiku · ‎2022-02-14

Hi Peter.. I expect frequency to be 900KHZ..

WF=Waveform i meant.

Current required is ~200mA

Still i see some ripple.

Peter BENSCH · ‎2022-02-14

The ST1S10 is a switching regulator with a free-running oscillator whose frequency accuracy cannot be compared to a crystal oscillator. In the datasheet, page 9 of the ST1S10, the frequency range is given when SYNC is connected to GND:

PWM fs - PWM switching frequency: min 0.7, typ 0.9, max 1.1 MHz.

This specification corresponds to a permissible deviation of ±200kHz, whereby your measured 980kHz are perfectly within the tolerance range.

Ripple: is typical to a greater or lesser extent in switching regulators by principle. However, you can minimise the ripple by following the instructions in the datasheet, e.g. using ceramic capacitors with low ESR and optimising the layout, see section 5.3.

Regards

/Peter

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Peter BENSCH · ‎2022-02-14

If the problem is resolved, please mark this topic as answered by selecting Select as best. This will help other users find that answer faster.

/Peter

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