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PowerSTEP01 VDDIO Connection

bmkc
Associate

Hi,

We are using the chip PowerSTEP01 in our design. In the datasheet, it is mentioned in the application diagram that the VDDIO pin can be powered from the VREG pin. However, the X-NUCLEO IHM03A1 evaluation board design shows that it is powered externally. Which one is the correct way of doing it? Are there any problems or limitations in powering the VDDIO from the internal regulator?

 

Best Regards,

Biju

1 ACCEPTED SOLUTION

Accepted Solutions
Peter BENSCH
ST Employee

Welcome @bmkc, to the community!

There is an internal LDO behind the pin VCCREG, which generates the 3.3V from the voltage at VCCREG, which is fed out at the pin VREG. However, if you want to supply VREG externally with 3.3V, you must connect VCCREG and VREG together and then apply this external voltage there (see data sheet, section 7.19, under fig 15).

It is therefore not a question of one of the two options being more correct, but of application variants.

Does it answer your question?

Regards
/Peter

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

2 REPLIES 2
Peter BENSCH
ST Employee

Welcome @bmkc, to the community!

There is an internal LDO behind the pin VCCREG, which generates the 3.3V from the voltage at VCCREG, which is fed out at the pin VREG. However, if you want to supply VREG externally with 3.3V, you must connect VCCREG and VREG together and then apply this external voltage there (see data sheet, section 7.19, under fig 15).

It is therefore not a question of one of the two options being more correct, but of application variants.

Does it answer your question?

Regards
/Peter

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
bmkc
Associate

Hi Peter,

Thank you for your reply. Yes, it does answer my question.
Regards,
Biju