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LIS2DUXS12 VDDIO w.r.t. VDD and schematic sanity check

justenoughducks
Associate

Hello,

I am developing a board with the LIS2DUXS12 accelero.

During testing after assembly, I saw that there was no reaction to I2C communication. Other devices on the bus work fine, with a logic analyzer I have seen that there is indeed traffic sent to 0x18.

 

I desoldered the component and saw that during assembly, was too little paste on the VDDIO and the SCL pin. I corrected it and resoldered the component and saw there was good contact under the microscope. I have connected the STEVAL$MKI235AA to the pins and that responds correctly.

I still see the same behavior, so my first question is this:

1. Are VDD and VDDIO completely isolated from each other such that VDD won't internally be connected to VDDIO in the event of a bad connection to VDDIO, the digital interface pins are in danger of being damaged?

2. I also am looking for a sanity check of my schematic. I have only 1uF + 100nF on the supply as 10uF seems extremely overkill for pulling <50uA and adds to the power rail capacitance, affecting inrush current (in very small PPG applications, often the bus capacitance can be a problem point for tiny DC/DC regulators).

NOTE: In this schematic picture, ADDR0 is left floating as it is a development board to have the flexibility of tying it to VDD or GND. 1uF bulk capacitance not pictures

justenoughducks_0-1745926040276.png

I would appreciate if someone could sanity check my schematic to make sure that the assembly VDDIO floating pin likely damaged the interface and not that I simply made a mistake in my schematic that I can easily solve.

 

Thank you for your time

1 REPLY 1
Federica Bossi
ST Employee

Hi @justenoughducks ,

 

VDD and VDDIO are connected via internal ESD diodes to avoid issue during soldering.
In sent schematic pin 2 (CS) and pin 3 (SDO/SA0) are floating. To use I2C is mandatory to put CS at high level and SA0 to GND or VDDIO according the desiderata I2C address.
Once the I2C is selected, please verify the power up sequence as described at page 14-15 of datasheet.

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