L9825 SPI INTERFACE TIMING related concerns

[Deva]

I have following three concerns related to SPI interface timing of L9825 low side driver IC. Please refer the image below.

1. Do we really need to toggle the clock signal within 100ns after NCS changed from High to low. If this 100ns is exceeded what would be response of driver IC in the SPI command recognition?

2. Why thcld is specified as Max 20ns instead of Min 20ns? Because it is always depends on the operating SCK period.

3.thclch is specified as Min 150ns. So, do we really need to bring SCK to logic high after NCS changed to logic high? If not what would be the behaviour of low side driver SPI interface recognition?

[Peter BENSCH]

Welcome @Deva, to the community!

You have already asked this question at the personal Online Support OLS with the case number 00232563, but they need some time to answer it together with the division. However, you won't speed up the process at all if you ask the same question here in the community - it's mainly users like you who are here trying to help each other.

Can I ask you to be patient until OLS has responded?

Alternatively, you can also contact your local distributor, who will also be happy to help you technically.

Regards
/Peter