20ns Pulses on MISO Line when Slave is not Programmed to Transmit

[melek_g]

Hi, 

I am using two STM23F303 Discovery Borads.

My application is as follows:

The two boards communicate via SPI.

Every two seconds the master boards send a uint8 message to the slave.

Upon receiving the message, the slave board shall light up some LEDs depending on the sent message.

This is a snippet of the code flashed to the slave board:

   while (FOREVER)
   {
      // When you receive a message from
      if (HAL_SPI_Receive(&hspi1, &u8SpiMsg, U16_NUM_BYTES, HAL_MAX_DELAY) == HAL_OK)
      {
         // Set/Reset corresponding LED pins via their control bits in BSRR register
         GPIOE->BSRR = ...........;
      }
   }

This is the configuration of the SPI: 

ˆ Mode - Full-Duplex Master/Slave
ˆ Hardware NSS Signal - Hardware NSS Input Signal
ˆ Frame Format - Motorola
ˆ Data Size - 8 bit
ˆ First Bit - MSB First
ˆ Prescaler (for Baud Rate) - 8
ˆ Clock Polarity - low
ˆ Clock Phase - 1 Edge
ˆ CRC Calculation - disable
ˆ NSSP Mode - Disable

The application works, but when I hooked up a logic analyser (saleae logic 8) to inspect the SPI communication, I saw that the MISO line is not always idle.

Some pulses of 20ns are observed on the MISO line whenever the slave sends a message, as shown in the following screenshots:

I don't understand why the MISO isn't idle when the slave is not sending anything? What is causing the 20ns pulses ?

[AScha.3 · Accepted solution]

Hi,

probably you see just an artifact from capacitive coupling clk -> miso , as your "spike" is exactly at the rising edge of the clock.

So have better isolation of the lines to reduce the crosstalk .

+

And use a high speed scope to see the real crosstalk/pulses - if you like .

A simple logic analyzer connected with unscreened signal wires is not useful for assessing conduction/crosstalk effects.

[Andrew Neil]

---

@AScha.3 wrote:

se a high speed scope to see the real crosstalk/pulses.

---

Absolutely!

@melek_g you always need to use a 'scope first to confirm that the signal is good & clean.

If the signal is not clean, a logic analyser will give misleading results ...

#ScopeFirst #ScopeThenLogicAnalyser

[melek_g]

Hi AScha,

I previously put the logic analyser probes for MISO, MOSI and the CLK all on the master board pins (so they were very close to each other)

Upon reading your post, I move the Probe of the MISO line (where the pulses where observed) to the MISO pin on the slave to introduce more distance between it and the clock probe.

And it worked! No more pulses were observed.

Thanks for your time.

Melek

[melek_g]

Unfortunately, I don't have a scope in the lab yet.

But thanks a lot for the advice. I'll definitely do that when I get one!