If pullup is enabled on gpio for SPI Clock, does pullup have any effect while spi is enabled?

[AMacd.1]

Say I am operating as master with CPOL=1.  Because the NSS pin seems to lag the enable bit (SPE) slightly, my logic analyzer always barfs on the first SPI packet because the clock is in the wrong state.

So, I set the GPIO to have a pullup on the clock in CubeMX and the problem goes away - as soon as the init functions run, the clock goes high and stays that way until the first SPI transmit.  Also, the clock stays high after the end of the transfer if the SPI is disabled in the callback function.

My only concern is for power consumption: It is obvious that the pullup gets applied when the SPI is disabled but I don't know is if the pullup applied all the time even when the alternate mode of the GPIO is set, i.e. is the pullup still applied at the pin when the SPI is enabled?  Do clock pulses during an SPI transaction work against the pullup?

[TDK]

Yes, it's still applied and will pull extra current while the pin is driven low.

You can enable the peripheral before sending the first transaction which will set SCK to the correct value. Doing a transaction with CS kept high will also do this.

[AMacd.1]

Thanks @TDK, so do you mean doing something like this?

void Spi2Tx(const uint8_t *Buffer, size_t Len)
{
  TransferState = TransferWait;
  __HAL_SPI_ENABLE(&hspi2);
  HAL_GPIO_WritePin(NSS_GPIO_Port, NSS_Pin, GPIO_PIN_RESET);
  if(HAL_SPI_Transmit_DMA(&hspi2, Buffer, Len) != HAL_OK)
  {
    Error_Handler();
  }

  while (TransferState == TransferWait)
  {
  }

  switch(TransferState)
  {
    case TransferComplete :
      break;
    default :
      Error_Handler();
      break;
  }
}

void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
  HAL_GPIO_WritePin(NSS_GPIO_Port, NSS_Pin, GPIO_PIN_SET);
  __HAL_SPI_DISABLE(hspi);
  TransferState = TransferComplete;
}

However, I don't understand what you mean by "Doing a transaction with CS kept high will also do this."  Can you please elaborate?  Is CS == NSS?  What does this pin have to do with the SPI peripheral when using software control of NSS (i.e. SSM=1)?

Edit: add missing initialization of TransferState

Edit 2: Changed question about "CS kept high."

[TDK]

You should put a delay between enabling the peripheral (which sets SCK to the correct value) and the first transaction. Typically there is a timing requirement here.

> However, I don't understand what you mean by "Doing a transaction with CS kept high will also do this."  How can I do that when the GPIO Mode for the clock pin is set to alternate function in CubeMX?

You are controlling CS, so do a transaction without setting it low. CS and NSS refer to the same pin. Presumably you set it high during pin initialization.

uint8_t data = 0;
HAL_SPI_Transmit(&hspi2, &data, 1, HAL_MAX_DELAY);

[AMacd.1]

 @TDK, additional questions:

1. If the SPI is disabled (SPE=0), and there is no pullup or pulldown, is the GPIO in analog mode or input?

2. What happens if the SPI is enabled (SPE=1, SSM=1, SSOE=0) and there is no transaction under way (i.e. FIFOs are empty and interrupts are disabled)?  Does the SPI draw more power when enabled than when disabled?

[TDK]

1) Input

2) An enabled peripheral draws more power than a disabled peripheral.

[AMacd.1]

Frankly @TDK, I can't imagine any application where CS is always high and I don't understand how keeping CS always high has any effect on the state of SCLK when SSM=1 (unless there's some hidden magic that the RM doesn't discuss!)

I assume then, for optimal optimal power consumption, the procedure would be to do the following:

Step A. Enable pullups on all the SPI pins (CubeMX) so that the pullups are already enabled at system initialization.

Step B. At the start of a transaction, 

1. Enable the SPI (SPE=1).
2. Disable the pullups on the GPIO pins.
3. Set NSS low (enables the slave's output pin - MISO).
4. Perform the transaction (HAL_SPI_Transmit...).

Step C. When the transaction is complete,

1. Set NSS high (the slave's ouput pin becomes high impedance).
2. Apply the pullups to the GPIO.
3. Disable the SPI (SPE=0).

Hopefully, this ensures,

• The SPI is disabled unless needed.
• The pullups control the IO termination when the SPI is disabled.
• The SPI peripheral controls the IO only when it is enabled.
• There is no circumstance where the IO is floating.

Does this make sense?

(Edit: change order of step C)

[TDK]

It enables the peripheral, as stated in the first reply.

[AMacd.1]

BTW, this procedure assumes CPOL=1.  If CPOL=0, pulldown on SCLK instead of pullup.

[AMacd.1]

"It enables the peripheral, as stated in the first reply."

I still don't follow.  Yes, I am aware that calling the function HAL_SPI_Transmit_DMA, for example, enables the peripheral and I can see that in the code for the HAL function.  What I don't understand is how this has anything to do with the state of CS.  Your statement, "Doing a transaction with CS kept high will also do this." is really like saying "Doing a transaction will enable the SPI, regardless of the state of CS."  I am not sure if this is pertinent to the question that I asked.