Unable to implement error detection features of STP16DP05

[shreyav-ext]

Please find attached the block diagram for the implemented circuit. I am working with a 4x5 LED array that requires error detection. The first three rows of the array are controlled by OUT0, OUT1, and OUT2 of the first STP16DP05 IC, while the remaining two rows are managed by another STP16DP05 IC connected in daisy chain. 

(Note: This setup is for evaluation purposes of a larger LED array setup)

The SPI protocol is used for data transmission between the MCU and the ICs. I would like to confirm whether the error timing diagram can be implemented using only the SPI clock, or if an external clock is necessary to meet the precise timing requirements for triggering the error mode.

Currently, I have implemented an external clock generated via a GPIO. A multiplexer alternates between the SPI clock and the GPIO-generated clock: the SPI clock is active during data transmission and reception, while the GPIO clock is enabled during the toggling of the OE and LE signals. Both the SPI and GPIO clock are synced in terms of clock cycles and frequency.

Although both the ICs seem to be entering error detection mode when less than 4 rows are enabled at once but fails to give valid outputs when more than 3 rows are enabled together, in this case, the output consistently returns zeros.

Additionally, when reading back errors, there appears to be a right bit shift in the error data which results in the loss of error bit of OUT0 from 1st IC. To address this, I have added an extra clock cycle before reading the error. This resolved the error bit position and the errors are obtained at correct positions after adding that extra clock cycle.

While I obtain partial outputs while less than 4 rows are enabled, the simultaneous enabling of all the LEDs for error detection is not working. 

Any advice on potential improvements or modifications would be appreciated to effectively implement the error detection features for multiple STP16DP05 ICs connected in daisy chain.

Please find attached the block diagram and the implementation of the modified timing diagram for your reference.

[Peter BENSCH]

Welcome @shreyav-ext, to the community!

Of course, the EDM (Error Detection Mode) does not require a different clock than that of SPI, switching via multiplexer is not necessary. Have you set all data bits for EDM to 1, as described in the data sheet, section 7.2 and in AN2478, section 3?

Regards
/Peter

[shreyav-ext]

1. But the SPI clock is only active when the master is transmitting or receiving data. How to synchronize the OE and LE signals with the SPI clock?

2. When we set all the data bits to 1, inconclusive error bits are being read. Does this mean that the IC is not entering into error mode?

3. However when we set data bits such that less than 4 columns of LED are being enabled, we are getting expected outputs.

This output is as expected because OUT2 of the first IC is enabled and OUT0 and OUT1 of the second IC is enabled. We have confirmed that this output is of error as when we short or open circuit any LED, the output of that LED changes to read a 0 indicating an error. 

 

4. Also if we do not add the extra clock pulse to modify the given error timing diagram, there is a right bit shift in the error bits from above which is not an expected output because we will lose OUT0 error bit of the first IC. This is in contradiction to the error timing diagram in the datasheet. Is there any particular reason for this right bit shift?

5. Like I have explained in the block diagram of the setup, we are using two ICs : 3 outputs of the first IC and 2 outputs of the 2nd IC for column control, rest all OUTs of both the ICs are left open (floating). Can this be a reason for inability to read back error correctly?